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STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F031F6P7TR

STID: C2053170TSSOP-20(4.4x6.4) · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F031F6P7TR (TSSOP-20(4.4x6.4))1BOOT02PF0OSC IN -_3PF1OSC OUT -4NRST5VDDA6PA07PA18PA29PA310PA420PA14 (SWCLK)19PA13 (SWDIO)18PA1017PA916VDD15VSS14PB113PA712PA611PA5Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1BOOT0IInput-Only Pin BOOT0 (General)
2PF0OSC IN -_ (PF0)I/OMultiplexed I/O & Peripheral Pin PF0OSC IN -_ (PF0) (RTC/CLK)
3PF1OSC OUT -_ (PF1)I/OMultiplexed I/O & Peripheral Pin PF1OSC OUT -_ (PF1) (RTC/CLK)
4NRSTISystem Enable & Hardware Reset (NRST)
5VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
6PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
8PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
9PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
10PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
11PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
12PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
13PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
14PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
15VSSGNDGround Reference Pin (VSS)
16VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
17PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C, PWM)
18PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, I2C, PWM)
19PA13 (SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13 (SWDIO) (SWD/JTAG)
20PA14 (SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14 (SWCLK) (UART, SWD/JTAG)
PIN 1 BOOT0
I
Input-Only Pin BOOT0 (General)
Design note: Alt: Bootmemoryselection
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F031F6P7TR (ST · TSSOP-20(4.4x6.4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) - 4. Package Dimensions (D×E×A)
TSSOP-20(4.4x6.4) · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for STM32F031
P25 · p25_fig02EXACT PACKAGE
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Figure 8. TSSOP20 package pinout 7RSYLHZ
Figure 8. TSSOP20 package pinout 7RSYLHZ
P96 · p96_fig01EXACT PACKAGE
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Figure 46.TSSOP20 package outline
Figure 46.TSSOP20 package outline
P97 · p97_fig01EXACT PACKAGE
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Figure 47. Recommended footprint for TSSOP20 package
Figure 47. Recommended footprint for TSSOP20 package
P1 · p01_fig011253×502px
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — • CRC calculation unit
• CRC calculation unit
P25 · p25_fig011546×961px
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Figure 7. WLCSP25 package pinout
Figure 7. WLCSP25 package pinout
P37 · p37_fig011546×1362px
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Figure 12. Power supply scheme
Figure 12. Power supply scheme
P37 · p37_fig01P37
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Datasheet Page 37 (p37_fig01)
Datasheet Page 37 (p37_fig01)
P56 · p56_fig011546×718px
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Figure 16. Typical application with an 8 MHz crystal
Figure 16. Typical application with an 8 MHz crystal
P73 · p73_fig011751×902px
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Figure 24. ADC accuracy characteristics
Figure 24. ADC accuracy characteristics
P73 · p73_fig021546×667px
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Figure 25. Typical connection diagram using the ADC
Figure 25. Typical connection diagram using the ADC
P82 · p82_fig011546×988px
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Figure 32. Recommended footprint for LQFP48 package
Figure 32. Recommended footprint for LQFP48 package
P85 · p85_fig011875×1196px
STM32F031F6P7TR (TSSOP-20(4.4x6.4)) — Figure 35. Recommended footprint for LQFP32 package
Figure 35. Recommended footprint for LQFP32 package
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (STM32F031F6P7TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F031F6P7TR (TSSOP-20(4.4x6.4)) is a 20-pin embedded microcontroller unit (mcu) featuring a 6.50 × 4.40 × 1.20 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
6 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.20 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20(4.4x6.4))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20(4.4x6.4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20(4.4x6.4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F031F6P7TR (TSSOP-20(4.4x6.4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F031F6P7TR (TSSOP-20(4.4x6.4))?

Manufactured by ST, the STM32F031F6P7TR is housed in a TSSOP-20(4.4x6.4) package with 20 pins and a 0.65 mm lead pitch. Key pins include: 1 (BOOT0: Input-Only Pin BOOT0 (General)), 2 (PF0OSC IN -_ (PF0): Multiplexed I/O & Peripheral Pin PF0OSC IN -_ (PF0) (RTC/CLK)), 3 (PF1OSC OUT -_ (PF1): Multiplexed I/O & Peripheral Pin PF1OSC OUT -_ (PF1) (RTC/CLK)), 4 (NRST: System Enable & Hardware Reset (NRST)), 5 (VDDA: Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))), 6 (PA0: Multiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32F031F6P7TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F031F6P7TR (TSSOP-20(4.4x6.4)) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F031F6P7TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F031F6P7TR (ST, TSSOP-20(4.4x6.4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & STM32F031 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
2PF0OSC IN -_ (PF0)Digital_IOSignal terminal PF0OSC IN -_ (PF0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF0OSC IN -_ (PF0). Supported peripheral buses: RTC/CLK.
3PF1OSC OUT -_ (PF1)Digital_IOSignal terminal PF1OSC OUT -_ (PF1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF1OSC OUT -_ (PF1). Supported peripheral buses: RTC/CLK.
4NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
5VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
6PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
8PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
9PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
10PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC.
11PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
12PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC, PWM.
13PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
14PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
15VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
16VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
17PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, PWM.
18PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C, PWM.
19PA13 (SWDIO)Digital_IOSignal terminal PA13 (SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (SWDIO). Supported peripheral buses: SWD/JTAG.
20PA14 (SWCLK)Digital_IOSignal terminal PA14 (SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (SWCLK). Supported peripheral buses: UART, SWD/JTAG.
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