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STM32L011E4Y6TR (WLCSP-25) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L011E4Y6TR

STID: C2052908WLCSP-25 · 25 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L011E4Y6TR (WLCSP-25)A1PA13A2PA14A3PB6A4PB7A5PB9 BOOT0 -B1PA9B2PB3B3PA4B4PA1B5PC14 - OSC32C1PA8C2PA10C3PA7E5PA0CK IN -_E4PA3E3PA6E2PB0E1VSSD5NRSTD4PA2D3PA5D2PB1D1VDDC5PC15 - OSC32C4VDDAGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
A1A2A3A4A5B1B2B3B4B5C1C2C3C4C5D1D2D3D4D5E1E2E3E4E5E=2.00mm · Pitch e=0.40mmD=2.00mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.00mm × 2.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (25/25)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SPI, I2C, SWD/JTAG)
A2PA14I/OMultiplexed I/O & Peripheral Pin PA14 (UART, SPI, I2C, SWD/JTAG)
A3PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C, PWM)
A4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C, PWM)
A5PB9 BOOT0 -I/OMultiplexed I/O & Peripheral Pin PB9 BOOT0 - (General)
B1PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C, RTC/CLK)
B2PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, PWM)
B3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, I2C, ADC)
B4PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, I2C, ADC, PWM)
B5PC14 - OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)
C1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
C2PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, I2C, PWM, RTC/CLK)
C3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (UART, SPI, ADC)
C4VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
C5PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
D1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D2PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, SPI, ADC)
D3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
D4PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM, RTC/CLK)
D5NRSTISystem Enable & Hardware Reset (NRST)
E1VSSGNDGround Reference Pin (VSS)
E2PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM)
E3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
E4PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
E5PA0CK IN -_I/OMultiplexed I/O & Peripheral Pin PA0CK IN -_ (UART, ADC, PWM, RTC/CLK)
PIN A1 PA13
I/O
Multiplexed I/O & Peripheral Pin PA13 (SPI, I2C, SWD/JTAG)
Design note: Alt: SWDIO , LPTIM1_ETR , I2C1_SDA , SPI1_SCK , LPUART1_RX , COMP1_OUT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L011E4Y6TR (ST · WLCSP-25)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L011E4Y6TR (WLCSP-25) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L011E4Y6TR (WLCSP-25) - 2. Standard Pinout (Top View)
True package pinout (25 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L011E4Y6TR (WLCSP-25) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L011E4Y6TR (WLCSP-25) - 4. Package Dimensions (D×E×A)
WLCSP-25 · 2.00×2.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L011E4Y6TR (WLCSP-25) - 5. Recommended Land Pattern
IPC-7351B Footprint (25 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L011E4Y6TR (WLCSP-25) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for STM32L011
P1 · p01_fig01EXACT PACKAGE
STM32L011E4Y6TR (WLCSP-25) — • 4x peripherals communication interface
• 4x peripherals communication interface
P34 · p34_fig01EXACT PACKAGE
STM32L011E4Y6TR (WLCSP-25) — Figure 5. STM32L011x3/4 WLCSP25 pinout
Figure 5. STM32L011x3/4 WLCSP25 pinout
P100 · p100_fig01EXACT PACKAGE
STM32L011E4Y6TR (WLCSP-25) — Figure 38. WLCSP25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale
Figure 38. WLCSP25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale
P101 · p101_fig01EXACT PACKAGE
STM32L011E4Y6TR (WLCSP-25) — Figure 39. WLCSP25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale
Figure 39. WLCSP25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale
P33 · p33_fig011546×978px
STM32L011E4Y6TR (WLCSP-25) — Figure 3. STM32L011x3/4 LQFP32 pinout
Figure 3. STM32L011x3/4 LQFP32 pinout
P33 · p33_fig021546×1266px
STM32L011E4Y6TR (WLCSP-25) —          
         
P34 · p34_fig021546×1376px
STM32L011E4Y6TR (WLCSP-25) — 3$ 3$ 1567
3$ 3$ 1567
P34 · p34_fig01P34
STM32L011E4Y6TR (WLCSP-25) — Datasheet Page 34 (p34_fig01)
Datasheet Page 34 (p34_fig01)
P45 · p45_fig011555×1257px
STM32L011E4Y6TR (WLCSP-25) — Figure 12. Power supply scheme
Figure 12. Power supply scheme
P45 · p45_fig021546×586px
STM32L011E4Y6TR (WLCSP-25) — Figure 13. Current consumption measurement scheme
Figure 13. Current consumption measurement scheme
P45 · p45_fig01P45
STM32L011E4Y6TR (WLCSP-25) — Datasheet Page 45 (p45_fig01)
Datasheet Page 45 (p45_fig01)
P84 · p84_fig011546×705px
STM32L011E4Y6TR (WLCSP-25) — Figure 28. Typical connection diagram using the ADC
Figure 28. Typical connection diagram using the ADC
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (STM32L011E4Y6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L011E4Y6TR (WLCSP-25) is a 25-pin embedded microcontroller unit (mcu) featuring a 2.00 × 2.00 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.65 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.65 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
15 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
2.00 × 2.00 × 0.56 mm (A1=0.17 mm)
Package family: WLCSP (WLCSP-25)
Pin Count & Lead PitchN / e
25 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB9 BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol25 auto-grouped pins
OK
IPC-7351B Land Pattern25 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-25)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.00 × 2.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
25P / 25Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-25
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L011E4Y6TR (WLCSP-25)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L011E4Y6TR (WLCSP-25)?

Manufactured by ST, the STM32L011E4Y6TR is housed in a WLCSP-25 package with 25 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: A1 (PA13: Multiplexed I/O & Peripheral Pin PA13 (SPI, I2C, SWD/JTAG)), A2 (PA14: Multiplexed I/O & Peripheral Pin PA14 (UART, SPI, I2C, SWD/JTAG)), A3 (PB6: Multiplexed I/O & Peripheral Pin PB6 (UART, I2C, PWM)), A4 (PB7: Multiplexed I/O & Peripheral Pin PB7 (UART, I2C, PWM)), A5 (PB9 BOOT0 -: Multiplexed I/O & Peripheral Pin PB9 BOOT0 - (General)), B1 (PA9: Multiplexed I/O & Peripheral Pin PA9 (UART, I2C, RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32L011E4Y6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L011E4Y6TR (WLCSP-25) has a nominal body envelope of 2.00 × 2.00 mm, pitch e = 0.40 mm, and 25 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L011E4Y6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L011E4Y6TR (ST, WLCSP-25) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (25 pins) & STM32L011 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, SPI1_SCK. Supported peripheral buses: SPI, I2C, SWD/JTAG.
A2PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MISO. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG.
A3PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, PWM.
A4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C, PWM.
A5PB9 BOOT0 -Digital_IOSignal terminal PB9 BOOT0 - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9 BOOT0 -. Supported peripheral buses: General.
B1PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, RTC/CLK.
B2PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, PWM.
B3PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, I2C1_SCL. Supported peripheral buses: UART, SPI, I2C, ADC.
B4PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA. Supported peripheral buses: UART, I2C, ADC, PWM.
B5PC14 - OSC32_INDigital_IOSignal terminal PC14 - OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN. Supported peripheral buses: RTC/CLK.
C1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, PWM, RTC/CLK.
C2PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C, PWM, RTC/CLK.
C3PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI, ADC.
C4VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C5PC15 - OSC32_OUTDigital_IOSignal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK.
D1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D2PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI, ADC.
D3PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
D4PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
D5NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E2PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC, PWM.
E3PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC.
E4PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
E5PA0CK IN -_Digital_IOSignal terminal PA0CK IN -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0CK IN -_. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
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