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AT27C512R-45RU (28-SOIC) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT27C512R-45RU

MICROCHIPID: C2042844628-SOIC · 28 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT27C512R-45RU (28-SOIC)1DeviceType2A123A74A65A56A47A38A29A110A011O012O113O214GND28VCC27A1426A1325A824A923A1122OE#/VPP21A1020CE#19O718O617O516O415O3Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728E=18.30mm · Pitch e=1.27mmD=8.60mm-14-12-10-8-6-4-202468101214121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 18.30mm × 8.60mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DeviceTypeI/OMultiplexed I/O & Peripheral Pin DeviceType (General)
2A12I/OMultiplexed I/O & Peripheral Pin A12 (General)
3A7I/OMultiplexed I/O & Peripheral Pin A7 (General)
4A6I/OMultiplexed I/O & Peripheral Pin A6 (General)
5A5I/OMultiplexed I/O & Peripheral Pin A5 (General)
6A4I/OMultiplexed I/O & Peripheral Pin A4 (General)
7A3I/OMultiplexed I/O & Peripheral Pin A3 (General)
8A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
9A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
10A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
11O0I/OMultiplexed I/O & Peripheral Pin O0 (General)
12O1I/OMultiplexed I/O & Peripheral Pin O1 (General)
13O2I/OMultiplexed I/O & Peripheral Pin O2 (General)
14GNDGNDGround Reference Pin (GND)
15O3I/OMultiplexed I/O & Peripheral Pin O3 (General)
16O4I/OMultiplexed I/O & Peripheral Pin O4 (General)
17O5I/OMultiplexed I/O & Peripheral Pin O5 (General)
18O6I/OMultiplexed I/O & Peripheral Pin O6 (General)
19O7I/OMultiplexed I/O & Peripheral Pin O7 (General)
20CE#I/OMultiplexed I/O & Peripheral Pin CE# (General)
21A10I/OMultiplexed I/O & Peripheral Pin A10 (General)
22OE#/VPPI/OMultiplexed I/O & Peripheral Pin OE#/VPP (General)
23A11I/OMultiplexed I/O & Peripheral Pin A11 (General)
24A9I/OMultiplexed I/O & Peripheral Pin A9 (General)
25A8I/OMultiplexed I/O & Peripheral Pin A8 (General)
26A13I/OMultiplexed I/O & Peripheral Pin A13 (General)
27A14I/OMultiplexed I/O & Peripheral Pin A14 (General)
28VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
PIN 1 DeviceType
I/O
Multiplexed I/O & Peripheral Pin DeviceType (General)
Design note: Signal terminal DeviceType (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DeviceType. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: AT27C512R-45RU (MICROCHIP · 28-SOIC)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
AT27C512R-45RU (28-SOIC) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT27C512R-45RU (28-SOIC) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT27C512R-45RU (28-SOIC) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT27C512R-45RU (28-SOIC) - 4. Package Dimensions (D×E×A)
28-SOIC · 18.30×8.60mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT27C512R-45RU (28-SOIC) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT27C512R-45RU (28-SOIC) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for AT27C512R
P1 · p01_fig01652×503px
AT27C512R-45RU (28-SOIC) — AT27C512R
AT27C512R
P2 · p02_fig02922×729px
AT27C512R-45RU (28-SOIC) — 2.3 28-lead TSOP Top View - Type 1 | 8 9 10 11 12 13 14 | 28 27 26 25 24 23 22 21 20 19 18 17 16 15 | A15 | A12 | A7 A6 A5 A4 A3 | A10 CE O7 O6 O5 O4 O3 GND O2 O1 O0 A0 A1 A2 | OE/VPP | A11 | A9 A8 A13 A14 VCC | 1 2 3 4 5 6 7
2.3 28-lead TSOP Top View - Type 1 | 8 9 10 11 12 13 14 | 28 27 26 25 24 23 22 21 20 19 18 17 16 15 | A15 | A12 | A7 A6 A5 A4 A3 | A10 CE O7 O6 O5 O4 O3 GND O2 O1 O0 A0 A1 A2 | OE/VPP | A11 | A9 A8 A13 A14 VCC | 1 2 3 4 5 6 7
P13 · p13_fig012128×2773px
AT27C512R-45RU (28-SOIC) — 13 | 0015O-EPROM-12/07 | AT27C512R | 19.5 28R - SOIC | A 2.39 - 2.79 | A1 0.050 - 0.356 | D 18.00 - 18.50 Note 1 | E 11.70 - 12.50 | E1 8.59 - 8.79 Note 1 | B 0.356 - 0.508 | C 0.203 - 0.305 | L 0.94 - 1.27 | e 1.27 TYP | PIN 1 | 0º ~ 8º |
13 | 0015O-EPROM-12/07 | AT27C512R | 19.5 28R - SOIC | A 2.39 - 2.79 | A1 0.050 - 0.356 | D 18.00 - 18.50 Note 1 | E 11.70 - 12.50 | E1 8.59 - 8.79 Note 1 | B 0.356 - 0.508 | C 0.203 - 0.305 | L 0.94 - 1.27 | e 1.27 TYP | PIN 1 | 0º ~ 8º |
P13 · p13_fig01P13
AT27C512R-45RU (28-SOIC) — Datasheet Page 13 (p13_fig01)
Datasheet Page 13 (p13_fig01)
P14 · p14_fig012124×2747px
AT27C512R-45RU (28-SOIC) — 14 | 0015O-EPROM-12/07 AT27C512R | 19.6 28T - TSOP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) C 28T | 12/06/02 | PIN 1 | 0º ~ 5º | D1
14 | 0015O-EPROM-12/07 AT27C512R | 19.6 28T - TSOP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) C 28T | 12/06/02 | PIN 1 | 0º ~ 5º | D1
P2 · p02_fig01All Packages in PDF
AT27C512R-45RU (28-SOIC) — O0
O0
P11 · p11_fig01All Packages in PDF
AT27C512R-45RU (28-SOIC) — 11 | 0015O-EPROM-12/07 | AT27C512R | Packaging Information | 19.3 32J - PLCC | DRAWING NO. REV. 2325 Orchard Parkway San Jose, CA 95131 R | TITLE | 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B 32J | 10/04/01 | 1.14(0.045) X 45˚ PIN
11 | 0015O-EPROM-12/07 | AT27C512R | Packaging Information | 19.3 32J - PLCC | DRAWING NO. REV. 2325 Orchard Parkway San Jose, CA 95131 R | TITLE | 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B 32J | 10/04/01 | 1.14(0.045) X 45˚ PIN

Technical Specifications & Part Details (AT27C512R-45RU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT27C512R-45RU (28-SOIC) is a 28-pin standard electronic & interconnect component featuring a 18.30 × 8.60 × 2.45 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
5 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
18.30 × 8.60 × 2.45 mm (A1=0.20 mm)
Package family: SOIC (28-SOIC)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (28-SOIC)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
18.30 × 8.60 mm
Height (A) & Pitch (e)IPC-7351B
A=2.45mm · e=1.27mm
Pad Size (W × L)Level B
0.70 × 2.91 mm
Pins / Total PadsTopology
28P / 28Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
28-SOIC
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT27C512R-45RU (28-SOIC)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT27C512R-45RU (28-SOIC)?

Manufactured by MICROCHIP, the AT27C512R-45RU is housed in a 28-SOIC package with 28 pins and a 1.27 mm lead pitch. Key pins include: 1 (DeviceType: Multiplexed I/O & Peripheral Pin DeviceType (General)), 2 (A12: Multiplexed I/O & Peripheral Pin A12 (General)), 3 (A7: Multiplexed I/O & Peripheral Pin A7 (General)), 4 (A6: Multiplexed I/O & Peripheral Pin A6 (General)), 5 (A5: Multiplexed I/O & Peripheral Pin A5 (General)), 6 (A4: Multiplexed I/O & Peripheral Pin A4 (General)).

What are the IPC-7351B PCB Footprint dimensions for AT27C512R-45RU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT27C512R-45RU (28-SOIC) has a nominal body envelope of 8.60 × 18.30 mm, pitch e = 1.27 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT27C512R-45RU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT27C512R-45RU (MICROCHIP, 28-SOIC) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & AT27C512R Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DeviceTypeDigital_IOSignal terminal DeviceType (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DeviceType. Supported peripheral buses: General.
2A12Digital_IOSignal terminal A12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A12. Supported peripheral buses: General.
3A7Digital_IOSignal terminal A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7. Supported peripheral buses: General.
4A6Digital_IOSignal terminal A6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6. Supported peripheral buses: General.
5A5Digital_IOSignal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
6A4Digital_IOSignal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
7A3Digital_IOSignal terminal A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
8A2Digital_IOSignal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
9A1Digital_IOSignal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
10A0Digital_IOSignal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
11O0Digital_IOSignal terminal O0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O0. Supported peripheral buses: General.
12O1Digital_IOSignal terminal O1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O1. Supported peripheral buses: General.
13O2Digital_IOSignal terminal O2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O2. Supported peripheral buses: General.
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15O3Digital_IOSignal terminal O3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O3. Supported peripheral buses: General.
16O4Digital_IOSignal terminal O4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O4. Supported peripheral buses: General.
17O5Digital_IOSignal terminal O5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O5. Supported peripheral buses: General.
18O6Digital_IOSignal terminal O6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O6. Supported peripheral buses: General.
19O7Digital_IOSignal terminal O7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O7. Supported peripheral buses: General.
20CE#Digital_IOSignal terminal CE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CE#. Supported peripheral buses: General.
21A10Digital_IOSignal terminal A10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A10. Supported peripheral buses: General.
22OE#/VPPDigital_IOSignal terminal OE#/VPP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OE#/VPP. Supported peripheral buses: General.
23A11Digital_IOSignal terminal A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A11. Supported peripheral buses: General.
24A9Digital_IOSignal terminal A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A9. Supported peripheral buses: General.
25A8Digital_IOSignal terminal A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A8. Supported peripheral buses: General.
26A13Digital_IOSignal terminal A13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A13. Supported peripheral buses: General.
27A14Digital_IOSignal terminal A14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A14. Supported peripheral buses: General.
28VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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