ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1)?

Manufactured by MICROCHIP, the ZL30291LDG1 is housed in a UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1 package with 101 pins and a 0.35 mm lead pitch. Key pins include: 1 (P1: Multiplexed I/O & Peripheral Pin P1 (General)), 2 (P2: Multiplexed I/O & Peripheral Pin P2 (General)), 3 (P3: Multiplexed I/O & Peripheral Pin P3 (General)), 4 (P4: Multiplexed I/O & Peripheral Pin P4 (General)), 5 (P5: Multiplexed I/O & Peripheral Pin P5 (General)), 6 (P6: Multiplexed I/O & Peripheral Pin P6 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for ZL30291LDG1?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.35 mm, and 101 copper pads plus a central exposed thermal pad (EPAD) of 5.10 × 5.10 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ZL30291LDG1?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ZL30291LDG1 (MICROCHIP, UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 8.00mm × 8.00mm · Pitch: 0.35mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (101/101)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	P1	I/O	Multiplexed I/O & Peripheral Pin P1 (General)
2	P2	I/O	Multiplexed I/O & Peripheral Pin P2 (General)
3	P3	I/O	Multiplexed I/O & Peripheral Pin P3 (General)
4	P4	I/O	Multiplexed I/O & Peripheral Pin P4 (General)
5	P5	I/O	Multiplexed I/O & Peripheral Pin P5 (General)
6	P6	I/O	Multiplexed I/O & Peripheral Pin P6 (General)
7	P7	I/O	Multiplexed I/O & Peripheral Pin P7 (General)
8	P8	I/O	Multiplexed I/O & Peripheral Pin P8 (General)
9	P9	I/O	Multiplexed I/O & Peripheral Pin P9 (General)
10	P10	I/O	Multiplexed I/O & Peripheral Pin P10 (General)
11	P11	I/O	Multiplexed I/O & Peripheral Pin P11 (General)
12	P12	I/O	Multiplexed I/O & Peripheral Pin P12 (General)
13	P13	I/O	Multiplexed I/O & Peripheral Pin P13 (General)
14	P14	I/O	Multiplexed I/O & Peripheral Pin P14 (General)
15	P15	I/O	Multiplexed I/O & Peripheral Pin P15 (General)
16	P16	I/O	Multiplexed I/O & Peripheral Pin P16 (General)
17	P17	I/O	Multiplexed I/O & Peripheral Pin P17 (General)
18	P18	I/O	Multiplexed I/O & Peripheral Pin P18 (General)
19	P19	I/O	Multiplexed I/O & Peripheral Pin P19 (General)
20	P20	I/O	Multiplexed I/O & Peripheral Pin P20 (General)
21	P21	I/O	Multiplexed I/O & Peripheral Pin P21 (General)
22	P22	I/O	Multiplexed I/O & Peripheral Pin P22 (General)
23	P23	I/O	Multiplexed I/O & Peripheral Pin P23 (General)
24	P24	I/O	Multiplexed I/O & Peripheral Pin P24 (General)
25	P25	I/O	Multiplexed I/O & Peripheral Pin P25 (General)
26	P26	I/O	Multiplexed I/O & Peripheral Pin P26 (General)
27	P27	I/O	Multiplexed I/O & Peripheral Pin P27 (General)
28	P28	I/O	Multiplexed I/O & Peripheral Pin P28 (General)
29	P29	I/O	Multiplexed I/O & Peripheral Pin P29 (General)
30	P30	I/O	Multiplexed I/O & Peripheral Pin P30 (General)
31	P31	I/O	Multiplexed I/O & Peripheral Pin P31 (General)
32	P32	I/O	Multiplexed I/O & Peripheral Pin P32 (General)
33	P33	I/O	Multiplexed I/O & Peripheral Pin P33 (General)
34	P34	I/O	Multiplexed I/O & Peripheral Pin P34 (General)
35	P35	I/O	Multiplexed I/O & Peripheral Pin P35 (General)
36	P36	I/O	Multiplexed I/O & Peripheral Pin P36 (General)
37	P37	I/O	Multiplexed I/O & Peripheral Pin P37 (General)
38	P38	I/O	Multiplexed I/O & Peripheral Pin P38 (General)
39	P39	I/O	Multiplexed I/O & Peripheral Pin P39 (General)
40	P40	I/O	Multiplexed I/O & Peripheral Pin P40 (General)
41	P41	I/O	Multiplexed I/O & Peripheral Pin P41 (General)
42	P42	I/O	Multiplexed I/O & Peripheral Pin P42 (General)
43	P43	I/O	Multiplexed I/O & Peripheral Pin P43 (General)
44	P44	I/O	Multiplexed I/O & Peripheral Pin P44 (General)
45	P45	I/O	Multiplexed I/O & Peripheral Pin P45 (General)
46	P46	I/O	Multiplexed I/O & Peripheral Pin P46 (General)
47	P47	I/O	Multiplexed I/O & Peripheral Pin P47 (General)
48	P48	I/O	Multiplexed I/O & Peripheral Pin P48 (General)
49	P49	I/O	Multiplexed I/O & Peripheral Pin P49 (General)
50	P50	I/O	Multiplexed I/O & Peripheral Pin P50 (General)
51	P51	I/O	Multiplexed I/O & Peripheral Pin P51 (General)
52	P52	I/O	Multiplexed I/O & Peripheral Pin P52 (General)
53	P53	I/O	Multiplexed I/O & Peripheral Pin P53 (General)
54	P54	I/O	Multiplexed I/O & Peripheral Pin P54 (General)
55	P55	I/O	Multiplexed I/O & Peripheral Pin P55 (General)
56	P56	I/O	Multiplexed I/O & Peripheral Pin P56 (General)
57	P57	I/O	Multiplexed I/O & Peripheral Pin P57 (General)
58	P58	I/O	Multiplexed I/O & Peripheral Pin P58 (General)
59	P59	I/O	Multiplexed I/O & Peripheral Pin P59 (General)
60	P60	I/O	Multiplexed I/O & Peripheral Pin P60 (General)
61	P61	I/O	Multiplexed I/O & Peripheral Pin P61 (General)
62	P62	I/O	Multiplexed I/O & Peripheral Pin P62 (General)
63	P63	I/O	Multiplexed I/O & Peripheral Pin P63 (General)
64	P64	I/O	Multiplexed I/O & Peripheral Pin P64 (General)
65	P65	I/O	Multiplexed I/O & Peripheral Pin P65 (General)
66	P66	I/O	Multiplexed I/O & Peripheral Pin P66 (General)
67	P67	I/O	Multiplexed I/O & Peripheral Pin P67 (General)
68	P68	I/O	Multiplexed I/O & Peripheral Pin P68 (General)
69	P69	I/O	Multiplexed I/O & Peripheral Pin P69 (General)
70	P70	I/O	Multiplexed I/O & Peripheral Pin P70 (General)
71	P71	I/O	Multiplexed I/O & Peripheral Pin P71 (General)
72	P72	I/O	Multiplexed I/O & Peripheral Pin P72 (General)
73	P73	I/O	Multiplexed I/O & Peripheral Pin P73 (General)
74	P74	I/O	Multiplexed I/O & Peripheral Pin P74 (General)
75	P75	I/O	Multiplexed I/O & Peripheral Pin P75 (General)
76	P76	I/O	Multiplexed I/O & Peripheral Pin P76 (General)
77	P77	I/O	Multiplexed I/O & Peripheral Pin P77 (General)
78	P78	I/O	Multiplexed I/O & Peripheral Pin P78 (General)
79	P79	I/O	Multiplexed I/O & Peripheral Pin P79 (General)
80	P80	I/O	Multiplexed I/O & Peripheral Pin P80 (General)
81	P81	I/O	Multiplexed I/O & Peripheral Pin P81 (General)
82	P82	I/O	Multiplexed I/O & Peripheral Pin P82 (General)
83	P83	I/O	Multiplexed I/O & Peripheral Pin P83 (General)
84	P84	I/O	Multiplexed I/O & Peripheral Pin P84 (General)
85	P85	I/O	Multiplexed I/O & Peripheral Pin P85 (General)
86	P86	I/O	Multiplexed I/O & Peripheral Pin P86 (General)
87	P87	I/O	Multiplexed I/O & Peripheral Pin P87 (General)
88	P88	I/O	Multiplexed I/O & Peripheral Pin P88 (General)
89	P89	I/O	Multiplexed I/O & Peripheral Pin P89 (General)
90	P90	I/O	Multiplexed I/O & Peripheral Pin P90 (General)
91	P91	I/O	Multiplexed I/O & Peripheral Pin P91 (General)
92	P92	I/O	Multiplexed I/O & Peripheral Pin P92 (General)
93	P93	I/O	Multiplexed I/O & Peripheral Pin P93 (General)
94	P94	I/O	Multiplexed I/O & Peripheral Pin P94 (General)
95	P95	I/O	Multiplexed I/O & Peripheral Pin P95 (General)
96	P96	I/O	Multiplexed I/O & Peripheral Pin P96 (General)
97	P97	I/O	Multiplexed I/O & Peripheral Pin P97 (General)
98	P98	I/O	Multiplexed I/O & Peripheral Pin P98 (General)
99	P99	I/O	Multiplexed I/O & Peripheral Pin P99 (General)
100	P100	I/O	Multiplexed I/O & Peripheral Pin P100 (General)
101	EPAD/GND	GND	Ground Reference Pin (EPAD/GND)

PIN 1 P1

I/O

Multiplexed I/O & Peripheral Pin P1 (General)

Design note: Signal terminal P1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) - 2. Standard Pinout (Top View)

True package pinout (101 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) - 4. Package Dimensions (D×E×A)

UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1 · 8.00×8.00mm · Pitch 0.35mmExpand ›

5. Recommended Land PatternLAND PATTERN

ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) - 5. Recommended Land Pattern

IPC-7351B Footprint (101 Pads)Expand ›

6. Application SchematicSCHEMATIC

ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)

Showing 1–12 of 14 uncropped original figures for ZL30291

P1 · p01_fig01376×200px

CK440Q Compliant Gen 6 PCIe and

P1 · p01_fig021615×937px

FIGURE 0-1: Functional Block Diagram.

P6 · p06_fig011777×1917px

FIGURE 1-1: 100-Lead 8 mm x 8 mm UQFN.

P12 · p12_fig01997×400px

FIGURE 2-3: Input Driven by a Push-Pull Differential Output.

P12 · p12_fig021184×440px

FIGURE 2-3: Input Driven by a Push-Pull Differential Output.

P13 · p13_fig011777×929px

FIGURE 2-5: Input Driven by a Single-Ended Output. 2.4 Clock Outputs

P13 · p13_fig02725×314px

ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) — FIGURE 2-6: Terminating Differential Outputs. 2.5 Termination of Unused Outputs Unused outputs should be left unconnected.

FIGURE 2-6: Terminating Differential Outputs. 2.5 Termination of Unused Outputs Unused outputs should be left unconnected.

P13 · p13_fig01P13

Datasheet Page 13 (p13_fig01)

P37 · p37_fig011011×551px

5.0 PACKAGE OUTLINE

P37 · p37_fig021361×816px

ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) — ●, ▲, ▼Pin one index is identified by a dot, delta up, or delta down (triangle mark). | Underbar (_) and/or Overbar (‾) symbol may not be to scale. | 3 e | 3 e

●, ▲, ▼Pin one index is identified by a dot, delta up, or delta down (triangle mark). | Underbar (_) and/or Overbar (‾) symbol may not be to scale. | 3 e | 3 e

P38 · p38_fig011604×2004px

 2021 - 2023 Microchip Technology Inc. and its subsidiaries DS20006463C-page 38

P38 · p38_fig01P38

Datasheet Page 38 (p38_fig01)

Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (ZL30291LDG1)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) is a 100-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.60 mm mechanical envelope (lead pitch e = 0.35 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 40°C to +85°C with integrated I2C interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

100 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

8.00 × 8.00 × 0.60 mm (A1=0.03 mm)

Package family: QFN (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1)

Pin Count & Lead PitchN / e

100 Pins | Pitch e = 0.35 mm (13.8 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

I2C

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol101 auto-grouped pins

IPC-7351B Land Pattern101 pads · Pitch 0.35mm

IPC-7525 60% Solder PasteEPAD 5.10×5.10mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

8.00 × 8.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.60mm · e=0.35mm

Pad Size (W × L)Level B

0.25 × 0.85 mm

Pins / Total PadsTopology

101P / 101Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1)?

Manufactured by MICROCHIP, the ZL30291LDG1 is housed in a UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1 package with 101 pins and a 0.35 mm lead pitch. Key pins include: 1 (P1: Multiplexed I/O & Peripheral Pin P1 (General)), 2 (P2: Multiplexed I/O & Peripheral Pin P2 (General)), 3 (P3: Multiplexed I/O & Peripheral Pin P3 (General)), 4 (P4: Multiplexed I/O & Peripheral Pin P4 (General)), 5 (P5: Multiplexed I/O & Peripheral Pin P5 (General)), 6 (P6: Multiplexed I/O & Peripheral Pin P6 (General)).

What are the IPC-7351B PCB Footprint dimensions for ZL30291LDG1?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ZL30291LDG1 (UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.35 mm, and 101 copper pads plus a central exposed thermal pad (EPAD) of 5.10 × 5.10 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ZL30291LDG1?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ZL30291LDG1 (MICROCHIP, UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (101 pins) & ZL30291 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	P1	Digital_IO	Signal terminal P1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1. Supported peripheral buses: General.
2	P2	Digital_IO	Signal terminal P2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2. Supported peripheral buses: General.
3	P3	Digital_IO	Signal terminal P3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3. Supported peripheral buses: General.
4	P4	Digital_IO	Signal terminal P4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4. Supported peripheral buses: General.
5	P5	Digital_IO	Signal terminal P5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5. Supported peripheral buses: General.
6	P6	Digital_IO	Signal terminal P6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P6. Supported peripheral buses: General.
7	P7	Digital_IO	Signal terminal P7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P7. Supported peripheral buses: General.
8	P8	Digital_IO	Signal terminal P8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P8. Supported peripheral buses: General.
9	P9	Digital_IO	Signal terminal P9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P9. Supported peripheral buses: General.
10	P10	Digital_IO	Signal terminal P10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P10. Supported peripheral buses: General.
11	P11	Digital_IO	Signal terminal P11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P11. Supported peripheral buses: General.
12	P12	Digital_IO	Signal terminal P12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P12. Supported peripheral buses: General.
13	P13	Digital_IO	Signal terminal P13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P13. Supported peripheral buses: General.
14	P14	Digital_IO	Signal terminal P14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P14. Supported peripheral buses: General.
15	P15	Digital_IO	Signal terminal P15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P15. Supported peripheral buses: General.
16	P16	Digital_IO	Signal terminal P16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P16. Supported peripheral buses: General.
17	P17	Digital_IO	Signal terminal P17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P17. Supported peripheral buses: General.
18	P18	Digital_IO	Signal terminal P18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P18. Supported peripheral buses: General.
19	P19	Digital_IO	Signal terminal P19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P19. Supported peripheral buses: General.
20	P20	Digital_IO	Signal terminal P20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P20. Supported peripheral buses: General.
21	P21	Digital_IO	Signal terminal P21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P21. Supported peripheral buses: General.
22	P22	Digital_IO	Signal terminal P22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P22. Supported peripheral buses: General.
23	P23	Digital_IO	Signal terminal P23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P23. Supported peripheral buses: General.
24	P24	Digital_IO	Signal terminal P24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P24. Supported peripheral buses: General.
25	P25	Digital_IO	Signal terminal P25 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P25. Supported peripheral buses: General.
26	P26	Digital_IO	Signal terminal P26 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P26. Supported peripheral buses: General.
27	P27	Digital_IO	Signal terminal P27 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P27. Supported peripheral buses: General.
28	P28	Digital_IO	Signal terminal P28 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P28. Supported peripheral buses: General.
29	P29	Digital_IO	Signal terminal P29 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P29. Supported peripheral buses: General.
30	P30	Digital_IO	Signal terminal P30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P30. Supported peripheral buses: General.
31	P31	Digital_IO	Signal terminal P31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P31. Supported peripheral buses: General.
32	P32	Digital_IO	Signal terminal P32 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P32. Supported peripheral buses: General.
33	P33	Digital_IO	Signal terminal P33 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P33. Supported peripheral buses: General.
34	P34	Digital_IO	Signal terminal P34 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P34. Supported peripheral buses: General.
35	P35	Digital_IO	Signal terminal P35 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P35. Supported peripheral buses: General.
36	P36	Digital_IO	Signal terminal P36 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P36. Supported peripheral buses: General.
37	P37	Digital_IO	Signal terminal P37 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P37. Supported peripheral buses: General.
38	P38	Digital_IO	Signal terminal P38 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P38. Supported peripheral buses: General.
39	P39	Digital_IO	Signal terminal P39 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P39. Supported peripheral buses: General.
40	P40	Digital_IO	Signal terminal P40 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P40. Supported peripheral buses: General.
41	P41	Digital_IO	Signal terminal P41 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P41. Supported peripheral buses: General.
42	P42	Digital_IO	Signal terminal P42 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P42. Supported peripheral buses: General.
43	P43	Digital_IO	Signal terminal P43 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P43. Supported peripheral buses: General.
44	P44	Digital_IO	Signal terminal P44 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P44. Supported peripheral buses: General.
45	P45	Digital_IO	Signal terminal P45 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P45. Supported peripheral buses: General.
46	P46	Digital_IO	Signal terminal P46 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P46. Supported peripheral buses: General.
47	P47	Digital_IO	Signal terminal P47 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P47. Supported peripheral buses: General.
48	P48	Digital_IO	Signal terminal P48 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P48. Supported peripheral buses: General.
49	P49	Digital_IO	Signal terminal P49 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P49. Supported peripheral buses: General.
50	P50	Digital_IO	Signal terminal P50 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P50. Supported peripheral buses: General.
51	P51	Digital_IO	Signal terminal P51 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P51. Supported peripheral buses: General.
52	P52	Digital_IO	Signal terminal P52 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P52. Supported peripheral buses: General.
53	P53	Digital_IO	Signal terminal P53 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P53. Supported peripheral buses: General.
54	P54	Digital_IO	Signal terminal P54 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P54. Supported peripheral buses: General.
55	P55	Digital_IO	Signal terminal P55 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P55. Supported peripheral buses: General.
56	P56	Digital_IO	Signal terminal P56 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P56. Supported peripheral buses: General.
57	P57	Digital_IO	Signal terminal P57 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P57. Supported peripheral buses: General.
58	P58	Digital_IO	Signal terminal P58 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P58. Supported peripheral buses: General.
59	P59	Digital_IO	Signal terminal P59 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P59. Supported peripheral buses: General.
60	P60	Digital_IO	Signal terminal P60 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P60. Supported peripheral buses: General.
61	P61	Digital_IO	Signal terminal P61 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P61. Supported peripheral buses: General.
62	P62	Digital_IO	Signal terminal P62 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P62. Supported peripheral buses: General.
63	P63	Digital_IO	Signal terminal P63 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P63. Supported peripheral buses: General.
64	P64	Digital_IO	Signal terminal P64 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P64. Supported peripheral buses: General.

4D Studio: ZL30291LDG1 Permalink: /part/C20297524 MICROCHIP UQFN-100_L8.0-W8.0-P0.50-BL-EP5.1 All Packages All Manufacturers