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CH372 (SSOP-20-208mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH372

WCHID: C19781SSOP-20-208mil · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH372 (SSOP-20-208mil)1RST2TXD3RXD4A05V36UD+7UD-8GND9XI10XO20VCC19CS#18GND17D716INT#15VCC14D413D312D211D1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=5.30mm · Pitch e=0.65mmD=7.20mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 5.30mm × 7.20mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
2TXDI/OMultiplexed I/O & Peripheral Pin TXD (UART)
3RXDI/OMultiplexed I/O & Peripheral Pin RXD (UART)
4A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
5V3PowerRegulated Power Output (V3 — 3.3V / 5.0V Standard Logic)
6UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
7UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
8GNDGNDGround Reference Pin (GND)
9XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
10XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
11D1I/OMultiplexed I/O & Peripheral Pin D1 (General)
12D2I/OMultiplexed I/O & Peripheral Pin D2 (General)
13D3I/OMultiplexed I/O & Peripheral Pin D3 (General)
14D4I/OMultiplexed I/O & Peripheral Pin D4 (General)
15VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
16INT#I/OMultiplexed I/O & Peripheral Pin INT# (General)
17D7I/OMultiplexed I/O & Peripheral Pin D7 (General)
18GNDGNDGround Reference Pin (GND)
19CS#I/OMultiplexed I/O & Peripheral Pin CS# (General)
20VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
PIN 1 RST
I/O
Multiplexed I/O & Peripheral Pin RST (General)
Design note: External reset input active high built -in pull -down , ,
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH372 (WCH · SSOP-20-208mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH372 (SSOP-20-208mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH372 (SSOP-20-208mil) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH372 (SSOP-20-208mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH372 (SSOP-20-208mil) - 4. Package Dimensions (D×E×A)
SSOP-20-208mil · 5.30×7.20mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH372 (SSOP-20-208mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH372 (SSOP-20-208mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for CH372
P1 · p01_fig01393×368px
CH372 (SSOP-20-208mil) — Package Width of Plastic Pitch of Pin Instruction of
Package Width of Plastic Pitch of Pin Instruction of
P1 · p01_fig01P1
CH372 (SSOP-20-208mil) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig011716×658px
CH372 (SSOP-20-208mil) — CH372 Datasheet (III) http://wch.cn 2 | resistor | 4 NOPU# Input | Disable pull-up resistor, active low, built-in weak pull-up | resistor. Each input pin has a pull-up resistor by default. When | NOPU# is set at low level, A3-A0, TXD and RX
CH372 Datasheet (III) http://wch.cn 2 | resistor | 4 NOPU# Input | Disable pull-up resistor, active low, built-in weak pull-up | resistor. Each input pin has a pull-up resistor by default. When | NOPU# is set at low level, A3-A0, TXD and RX
P2 · p02_fig01P2
CH372 (SSOP-20-208mil) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)

Technical Specifications & Part Details (CH372)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH372 (SSOP-20-208mil) is a 20-pin standard electronic & interconnect component featuring a 7.20 × 5.30 × 2.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.20 × 5.30 × 2.00 mm (A1=0.15 mm)
Package family: TSSOP (SSOP-20-208mil)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SSOP-20-208mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.20 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=2.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.60 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SSOP-20-208mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH372 (SSOP-20-208mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH372 (SSOP-20-208mil)?

Manufactured by WCH, the CH372 is housed in a SSOP-20-208mil package with 20 pins and a 0.65 mm lead pitch. Key pins include: 1 (RST: Multiplexed I/O & Peripheral Pin RST (General)), 2 (TXD: Multiplexed I/O & Peripheral Pin TXD (UART)), 3 (RXD: Multiplexed I/O & Peripheral Pin RXD (UART)), 4 (A0: Multiplexed I/O & Peripheral Pin A0 (General)), 5 (V3: Regulated Power Output (V3 — 3.3V / 5.0V Standard Logic)), 6 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)).

What are the IPC-7351B PCB Footprint dimensions for CH372?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH372 (SSOP-20-208mil) has a nominal body envelope of 5.30 × 7.20 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH372?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH372 (WCH, SSOP-20-208mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH372 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RSTDigital_IOSignal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
2TXDDigital_IOSignal terminal TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD. Supported peripheral buses: UART.
3RXDDigital_IOSignal terminal RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD. Supported peripheral buses: UART.
4A0Digital_IOSignal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
5V3Power_OutRegulated power output rail (V3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
7UD-Digital_IOSignal terminal UD- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
8GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
9XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
10XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
11D1Digital_IOSignal terminal D1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D1. Supported peripheral buses: General.
12D2Digital_IOSignal terminal D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D2. Supported peripheral buses: General.
13D3Digital_IOSignal terminal D3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D3. Supported peripheral buses: General.
14D4Digital_IOSignal terminal D4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D4. Supported peripheral buses: General.
15VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
16INT#Digital_IOSignal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General.
17D7Digital_IOSignal terminal D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D7. Supported peripheral buses: General.
18GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
19CS#Digital_IOSignal terminal CS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General.
20VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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