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AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT25010AY1-10YI-1.8

MICROCHIPID: C19574203MAP-8(3x4.9) · 9 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT25010AY1-10YI-1.8 (MAP-8(3x4.9))1CS#2SO3WP#4GND5SI9EP8VCC7HOLD#6SCKGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.812.77.62.5-2.5-7.6-12.7mm
2. 2D FOOTPRINT
123456789E=4.90mm · Pitch e=0.65mmD=3.00mm-4-3-2-101234543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.90mm × 3.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (9/9)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1CS#I/OMultiplexed I/O & Peripheral Pin CS# (General)
2SOI/OMultiplexed I/O & Peripheral Pin SO (General)
3WP#I/OMultiplexed I/O & Peripheral Pin WP# (General)
4GNDGNDGround Reference Pin (GND)
5SII/OMultiplexed I/O & Peripheral Pin SI (General)
6SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
7HOLD#I/OMultiplexed I/O & Peripheral Pin HOLD# (General)
8VCCPowerPower Supply Input (VCC — 2.7V to 5.5V)
9EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 CS#
I/O
Multiplexed I/O & Peripheral Pin CS# (General)
Design note: Signal terminal CS# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: AT25010AY1-10YI-1.8 (MICROCHIP · MAP-8(3x4.9))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) - 2. Standard Pinout (Top View)
True package pinout (9 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) - 4. Package Dimensions (D×E×A)
MAP-8(3x4.9) · 4.90×3.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) - 5. Recommended Land Pattern
IPC-7351B Footprint (9 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for AT25010
P1 · p01_fig01651×503px
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) — 1K (128x8)
1K (128x8)
P1 · p01_fig021434×720px
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) — Table 1. Pin Configuration | Pin Name Function | CS Chip Select | SCK Serial Data Clock | SI Serial Data Input | SO Serial Data Output | GND Ground | VCC Power Supply | WP Write Protect | HOLD Suspends Serial Input | 1 2 3 4 | 8 7 6 5 | CS
Table 1. Pin Configuration | Pin Name Function | CS Chip Select | SCK Serial Data Clock | SI Serial Data Input | SO Serial Data Output | GND Ground | VCC Power Supply | WP Write Protect | HOLD Suspends Serial Input | 1 2 3 4 | 8 7 6 5 | CS
P2 · p02_fig011229×1175px
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) — Figure 1. Block Diagram
Figure 1. Block Diagram
P16 · p16_fig012099×2596px
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) — 16 AT25010A/020A/040A | 3348H-SEEPR-9/04 | Packaging Information | 8P3 - PDIP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) | 01/09/02 | 8P3 B | C
16 AT25010A/020A/040A | 3348H-SEEPR-9/04 | Packaging Information | 8P3 - PDIP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) | 01/09/02 | 8P3 B | C
P16 · p16_fig01P16
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) — Datasheet Page 16 (p16_fig01)
Datasheet Page 16 (p16_fig01)
P17 · p17_fig012038×2583px
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) — AT25010A/020A/040A
AT25010A/020A/040A
P18 · p18_fig012099×2596px
AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) — 18 AT25010A/020A/040A | 3348H-SEEPR-9/04 | 8A2 - TSSOP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. | 5/30/02 | COMMON DIMENSIONS | (Unit of Measure = mm) | SYMBOL MIN NOM MAX NOTE | D 2.90 3.00 3.10 2, 5 | E 6.4
18 AT25010A/020A/040A | 3348H-SEEPR-9/04 | 8A2 - TSSOP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. | 5/30/02 | COMMON DIMENSIONS | (Unit of Measure = mm) | SYMBOL MIN NOM MAX NOTE | D 2.90 3.00 3.10 2, 5 | E 6.4

Technical Specifications & Part Details (AT25010AY1-10YI-1.8)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) is a 8-pin standard electronic & interconnect component featuring a 4.90 × 3.00 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.7V to 5.5V supply operation across 40°C to +85°C with integrated SPI interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.90 × 3.00 × 1.00 mm (A1=0.02 mm)
Package family: OTHER (MAP-8(3x4.9))
Pin Count & Lead PitchN / e
8 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol9 auto-grouped pins
OK
IPC-7351B Land Pattern9 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteEPAD 1.00×1.00mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (MAP-8(3x4.9))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.90 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.36 × 1.22 mm
Pins / Total PadsTopology
9P / 9Pad (CUSTOM_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
MAP-8(3x4.9)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT25010AY1-10YI-1.8 (MAP-8(3x4.9))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT25010AY1-10YI-1.8 (MAP-8(3x4.9))?

Manufactured by MICROCHIP, the AT25010AY1-10YI-1.8 is housed in a MAP-8(3x4.9) package with 9 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.7V to 5.5V. Key pins include: 1 (CS#: Multiplexed I/O & Peripheral Pin CS# (General)), 2 (SO: Multiplexed I/O & Peripheral Pin SO (General)), 3 (WP#: Multiplexed I/O & Peripheral Pin WP# (General)), 4 (GND: Ground Reference Pin (GND)), 5 (SI: Multiplexed I/O & Peripheral Pin SI (General)), 6 (SCK: Multiplexed I/O & Peripheral Pin SCK (SPI)).

What are the IPC-7351B PCB Footprint dimensions for AT25010AY1-10YI-1.8?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT25010AY1-10YI-1.8 (MAP-8(3x4.9)) has a nominal body envelope of 3.00 × 4.90 mm, pitch e = 0.65 mm, and 9 copper pads plus a central exposed thermal pad (EPAD) of 1.00 × 1.00 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT25010AY1-10YI-1.8?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT25010AY1-10YI-1.8 (MICROCHIP, MAP-8(3x4.9)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (9 pins) & AT25010 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1CS#Digital_IOSignal terminal CS# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General.
2SODigital_IOSignal terminal SO (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SO. Supported peripheral buses: General.
3WP#Digital_IOSignal terminal WP# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: WP#. Supported peripheral buses: General.
4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5SIDigital_IOSignal terminal SI (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SI. Supported peripheral buses: General.
6SCKDigital_IOSignal terminal SCK (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
7HOLD#Digital_IOSignal terminal HOLD# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: HOLD#. Supported peripheral buses: General.
8VCCPower_InPrimary positive power supply input (VCC) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
9EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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