| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | EN# | I/O | Multiplexed I/O & Peripheral Pin EN# (General) |
| 2 | DIN | I/O | Multiplexed I/O & Peripheral Pin DIN (General) |
| 3 | DIN# | I/O | Multiplexed I/O & Peripheral Pin DIN# (General) |
| 4 | VREF | Analog | Multiplexed I/O & Peripheral Pin VREF (General) |
| 5 | LOSLVL | I/O | Multiplexed I/O & Peripheral Pin LOSLVL (General) |
| 6 | GND | GND | Ground Reference Pin (GND) |
| 7 | LOS# | I/O | Multiplexed I/O & Peripheral Pin LOS# (General) |
| 8 | DOUT# | I/O | Multiplexed I/O & Peripheral Pin DOUT# (General) |
| 9 | DOUT | I/O | Multiplexed I/O & Peripheral Pin DOUT (General) |
| 10 | VCC | Power | Power Supply Input (VCC — 3.3V / 5.0V Standard Logic) |
| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit MSOP-10 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Manufactured by MICROCHIP, the SY88913KC is housed in a MSOP-10 package with 10 pins and a 0.50 mm lead pitch. Key pins include: 1 (EN#: Multiplexed I/O & Peripheral Pin EN# (General)), 2 (DIN: Multiplexed I/O & Peripheral Pin DIN (General)), 3 (DIN#: Multiplexed I/O & Peripheral Pin DIN# (General)), 4 (VREF: Multiplexed I/O & Peripheral Pin VREF (General)), 5 (LOSLVL: Multiplexed I/O & Peripheral Pin LOSLVL (General)), 6 (GND: Ground Reference Pin (GND)).
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SY88913KC (MSOP-10) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 10 copper pads.
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SY88913KC (MICROCHIP, MSOP-10) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | EN# | Digital_IO | Signal terminal EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: EN#. Supported peripheral buses: General. |
| 2 | DIN | Digital_IO | Signal terminal DIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN. Supported peripheral buses: General. |
| 3 | DIN# | Digital_IO | Signal terminal DIN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN#. Supported peripheral buses: General. |
| 4 | VREF | Analog | Signal terminal VREF (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF. Supported peripheral buses: General. |
| 5 | LOSLVL | Digital_IO | Signal terminal LOSLVL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LOSLVL. Supported peripheral buses: General. |
| 6 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 7 | LOS# | Digital_IO | Signal terminal LOS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LOS#. Supported peripheral buses: General. |
| 8 | DOUT# | Digital_IO | Signal terminal DOUT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT#. Supported peripheral buses: General. |
| 9 | DOUT | Digital_IO | Signal terminal DOUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT. Supported peripheral buses: General. |
| 10 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |