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AT28HC64BF-70PU (PDIP-28) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT28HC64BF-70PU

MICROCHIPID: C19434438PDIP-28 · 28 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT28HC64BF-70PU (PDIP-28)1NC2A123A74A65A56A47A38A29A110A011I/O012I/O113I/O214GND28VCC27WE#26NC25A824A923A1122OE#21A1020CE#19I/O718I/O617I/O516I/O415I/O3Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728E=14.10mm · Pitch e=2.54mmD=35.02mm-18-16-14-12-10-8-6-4-202468101214161827252321191715131197531-1-3-5-7-9-11-13-15-17-19-21-23-25-27mm
3. 3D CAD MODEL
Package Body: 14.10mm × 35.02mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NCI/OMultiplexed I/O & Peripheral Pin NC (General)
2A12I/OMultiplexed I/O & Peripheral Pin A12 (General)
3A7I/OMultiplexed I/O & Peripheral Pin A7 (General)
4A6I/OMultiplexed I/O & Peripheral Pin A6 (General)
5A5I/OMultiplexed I/O & Peripheral Pin A5 (General)
6A4I/OMultiplexed I/O & Peripheral Pin A4 (General)
7A3I/OMultiplexed I/O & Peripheral Pin A3 (General)
8A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
9A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
10A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
11I/O0I/OMultiplexed I/O & Peripheral Pin I/O0 (General)
12I/O1I/OMultiplexed I/O & Peripheral Pin I/O1 (General)
13I/O2I/OMultiplexed I/O & Peripheral Pin I/O2 (General)
14GNDGNDGround Reference Pin (GND)
15I/O3I/OMultiplexed I/O & Peripheral Pin I/O3 (General)
16I/O4I/OMultiplexed I/O & Peripheral Pin I/O4 (General)
17I/O5I/OMultiplexed I/O & Peripheral Pin I/O5 (General)
18I/O6I/OMultiplexed I/O & Peripheral Pin I/O6 (General)
19I/O7I/OMultiplexed I/O & Peripheral Pin I/O7 (General)
20CE#I/OMultiplexed I/O & Peripheral Pin CE# (General)
21A10I/OMultiplexed I/O & Peripheral Pin A10 (General)
22OE#I/OMultiplexed I/O & Peripheral Pin OE# (General)
23A11I/OMultiplexed I/O & Peripheral Pin A11 (General)
24A9I/OMultiplexed I/O & Peripheral Pin A9 (General)
25A8I/OMultiplexed I/O & Peripheral Pin A8 (General)
26NCI/OMultiplexed I/O & Peripheral Pin NC (General)
27WE#I/OMultiplexed I/O & Peripheral Pin WE# (General)
28VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
PIN 1 NC
I/O
Multiplexed I/O & Peripheral Pin NC (General)
Design note: Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: AT28HC64BF-70PU (MICROCHIP · PDIP-28)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
AT28HC64BF-70PU (PDIP-28) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT28HC64BF-70PU (PDIP-28) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT28HC64BF-70PU (PDIP-28) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT28HC64BF-70PU (PDIP-28) - 4. Package Dimensions (D×E×A)
PDIP-28 · 14.10×35.02mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT28HC64BF-70PU (PDIP-28) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT28HC64BF-70PU (PDIP-28) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for AT28HC64BF
P1 · p01_fig01652×503px
AT28HC64BF-70PU (PDIP-28) — 64K (8K x 8) High Speed Parallel EEPROM with Page Write and Software Data Protection
64K (8K x 8) High Speed Parallel EEPROM with Page Write and Software Data Protection
P2 · p02_fig01972×828px
AT28HC64BF-70PU (PDIP-28) — Note: PLCC package pins 1 and 17 are Don’t Connect.
Note: PLCC package pins 1 and 17 are Don’t Connect.
P15 · p15_fig012128×2749px
AT28HC64BF-70PU (PDIP-28) — 15 | 3648A-PEEPR-10/06 | AT28HC64BF | 30.2 28P6 - PDIP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) B 28P6 | 09/28/01 | PIN | 1 | E1 | A1 |
15 | 3648A-PEEPR-10/06 | AT28HC64BF | 30.2 28P6 - PDIP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) B 28P6 | 09/28/01 | PIN | 1 | E1 | A1 |
P15 · p15_fig01P15
AT28HC64BF-70PU (PDIP-28) — Datasheet Page 15 (p15_fig01)
Datasheet Page 15 (p15_fig01)
P17 · p17_fig012128×2749px
AT28HC64BF-70PU (PDIP-28) — 17 | 3648A-PEEPR-10/06 | AT28HC64BF | 30.4 28T - TSOP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) C 28T | 12/06/02 | PIN 1 | 0º ~ 5º |
17 | 3648A-PEEPR-10/06 | AT28HC64BF | 30.4 28T - TSOP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) C 28T | 12/06/02 | PIN 1 | 0º ~ 5º |
P14 · p14_fig01All Packages in PDF
AT28HC64BF-70PU (PDIP-28) — 14 | 3648A-PEEPR-10/06 AT28HC64BF | 30. Packaging Information | 30.1 32J - PLCC | DRAWING NO. REV. 2325 Orchard Parkway San Jose, CA 95131 R | TITLE | 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B 32J | 10/04/01 | 1.14(0.045) X 45˚ P
14 | 3648A-PEEPR-10/06 AT28HC64BF | 30. Packaging Information | 30.1 32J - PLCC | DRAWING NO. REV. 2325 Orchard Parkway San Jose, CA 95131 R | TITLE | 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B 32J | 10/04/01 | 1.14(0.045) X 45˚ P

Technical Specifications & Part Details (AT28HC64BF-70PU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT28HC64BF-70PU (PDIP-28) is a 28-pin standard electronic & interconnect component featuring a 35.02 × 14.10 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C - 85°C with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C - 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
5 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
35.02 × 14.10 × 4.20 mm (A1=0.51 mm)
Package family: DIP (PDIP-28)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-28)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
35.02 × 14.10 mm
Height (A) & Pitch (e)IPC-7351B
A=4.20mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
28P / 28Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PDIP-28
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT28HC64BF-70PU (PDIP-28)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT28HC64BF-70PU (PDIP-28)?

Manufactured by MICROCHIP, the AT28HC64BF-70PU is housed in a PDIP-28 package with 28 pins and a 2.54 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (A12: Multiplexed I/O & Peripheral Pin A12 (General)), 3 (A7: Multiplexed I/O & Peripheral Pin A7 (General)), 4 (A6: Multiplexed I/O & Peripheral Pin A6 (General)), 5 (A5: Multiplexed I/O & Peripheral Pin A5 (General)), 6 (A4: Multiplexed I/O & Peripheral Pin A4 (General)).

What are the IPC-7351B PCB Footprint dimensions for AT28HC64BF-70PU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT28HC64BF-70PU (PDIP-28) has a nominal body envelope of 14.10 × 35.02 mm, pitch e = 2.54 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT28HC64BF-70PU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT28HC64BF-70PU (MICROCHIP, PDIP-28) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & AT28HC64BF Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
2A12Digital_IOSignal terminal A12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A12. Supported peripheral buses: General.
3A7Digital_IOSignal terminal A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7. Supported peripheral buses: General.
4A6Digital_IOSignal terminal A6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6. Supported peripheral buses: General.
5A5Digital_IOSignal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
6A4Digital_IOSignal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
7A3Digital_IOSignal terminal A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
8A2Digital_IOSignal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
9A1Digital_IOSignal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
10A0Digital_IOSignal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
11I/O0Digital_IOSignal terminal I/O0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O0. Supported peripheral buses: General.
12I/O1Digital_IOSignal terminal I/O1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O1. Supported peripheral buses: General.
13I/O2Digital_IOSignal terminal I/O2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O2. Supported peripheral buses: General.
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15I/O3Digital_IOSignal terminal I/O3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O3. Supported peripheral buses: General.
16I/O4Digital_IOSignal terminal I/O4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O4. Supported peripheral buses: General.
17I/O5Digital_IOSignal terminal I/O5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O5. Supported peripheral buses: General.
18I/O6Digital_IOSignal terminal I/O6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O6. Supported peripheral buses: General.
19I/O7Digital_IOSignal terminal I/O7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O7. Supported peripheral buses: General.
20CE#Digital_IOSignal terminal CE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CE#. Supported peripheral buses: General.
21A10Digital_IOSignal terminal A10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A10. Supported peripheral buses: General.
22OE#Digital_IOSignal terminal OE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OE#. Supported peripheral buses: General.
23A11Digital_IOSignal terminal A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A11. Supported peripheral buses: General.
24A9Digital_IOSignal terminal A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A9. Supported peripheral buses: General.
25A8Digital_IOSignal terminal A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A8. Supported peripheral buses: General.
26NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
27WE#Digital_IOSignal terminal WE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WE#. Supported peripheral buses: General.
28VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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