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AT27C2048-15PC (PDIP-40) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT27C2048-15PC

MICROCHIPID: C19342555PDIP-40 · 40 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT27C2048-15PC (PDIP-40)1DeviceType2CE#3O154O145O136O127O118O109O910O811GND12O713O614O515O416O317O218O119O020OE#40VCC39PGM#38A1637A1536A1435A1334A1233A1132A1031A930GND29A828A727A626A525A424A323A222A121A0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.830.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940E=13.90mm · Pitch e=2.54mmD=50.26mm-22-20-18-16-14-12-10-8-6-4-2024681012141618202239373533312927252321191715131197531-1-3-5-7-9-11-13-15-17-19-21-23-25-27-29-31-33-35-37-39mm
3. 3D CAD MODEL
Package Body: 13.90mm × 50.26mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (40/40)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DeviceTypeI/OMultiplexed I/O & Peripheral Pin DeviceType (General)
2CE#I/OMultiplexed I/O & Peripheral Pin CE# (General)
3O15I/OMultiplexed I/O & Peripheral Pin O15 (General)
4O14I/OMultiplexed I/O & Peripheral Pin O14 (General)
5O13I/OMultiplexed I/O & Peripheral Pin O13 (General)
6O12I/OMultiplexed I/O & Peripheral Pin O12 (General)
7O11I/OMultiplexed I/O & Peripheral Pin O11 (General)
8O10I/OMultiplexed I/O & Peripheral Pin O10 (General)
9O9I/OMultiplexed I/O & Peripheral Pin O9 (General)
10O8I/OMultiplexed I/O & Peripheral Pin O8 (General)
11GNDGNDGround Reference Pin (GND)
12O7I/OMultiplexed I/O & Peripheral Pin O7 (General)
13O6I/OMultiplexed I/O & Peripheral Pin O6 (General)
14O5I/OMultiplexed I/O & Peripheral Pin O5 (General)
15O4I/OMultiplexed I/O & Peripheral Pin O4 (General)
16O3I/OMultiplexed I/O & Peripheral Pin O3 (General)
17O2I/OMultiplexed I/O & Peripheral Pin O2 (General)
18O1I/OMultiplexed I/O & Peripheral Pin O1 (General)
19O0I/OMultiplexed I/O & Peripheral Pin O0 (General)
20OE#I/OMultiplexed I/O & Peripheral Pin OE# (General)
21A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
22A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
23A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
24A3I/OMultiplexed I/O & Peripheral Pin A3 (General)
25A4I/OMultiplexed I/O & Peripheral Pin A4 (General)
26A5I/OMultiplexed I/O & Peripheral Pin A5 (General)
27A6I/OMultiplexed I/O & Peripheral Pin A6 (General)
28A7I/OMultiplexed I/O & Peripheral Pin A7 (General)
29A8I/OMultiplexed I/O & Peripheral Pin A8 (General)
30GNDGNDGround Reference Pin (GND)
31A9I/OMultiplexed I/O & Peripheral Pin A9 (General)
32A10I/OMultiplexed I/O & Peripheral Pin A10 (General)
33A11I/OMultiplexed I/O & Peripheral Pin A11 (General)
34A12I/OMultiplexed I/O & Peripheral Pin A12 (General)
35A13I/OMultiplexed I/O & Peripheral Pin A13 (General)
36A14I/OMultiplexed I/O & Peripheral Pin A14 (General)
37A15I/OMultiplexed I/O & Peripheral Pin A15 (General)
38A16I/OMultiplexed I/O & Peripheral Pin A16 (General)
39PGM#I/OMultiplexed I/O & Peripheral Pin PGM# (General)
40VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
PIN 1 DeviceType
I/O
Multiplexed I/O & Peripheral Pin DeviceType (General)
Design note: Signal terminal DeviceType (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DeviceType. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: AT27C2048-15PC (MICROCHIP · PDIP-40)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
AT27C2048-15PC (PDIP-40) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT27C2048-15PC (PDIP-40) - 2. Standard Pinout (Top View)
True package pinout (40 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT27C2048-15PC (PDIP-40) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT27C2048-15PC (PDIP-40) - 4. Package Dimensions (D×E×A)
PDIP-40 · 13.90×50.26mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT27C2048-15PC (PDIP-40) - 5. Recommended Land Pattern
IPC-7351B Footprint (40 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT27C2048-15PC (PDIP-40) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for AT27C2048
P1 · p01_fig01652×503px
AT27C2048-15PC (PDIP-40) — AT27C2048
AT27C2048
P1 · p01_fig02663×1034px
AT27C2048-15PC (PDIP-40) — NC
NC
P1 · p01_fig031361×857px
AT27C2048-15PC (PDIP-40) — 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P2 · p02_fig011668×720px
AT27C2048-15PC (PDIP-40) — Block Diagram | GND VPP | VCC DATA OUTPUTS | O0 - O15 | OE, CE AND PROGRAM LOGIC | Y DECODER | X DECODER | OUTPUT BUFFERS | Y-GATING | CELL MATRIX | IDENTIFICATION | A0 - A17 ADDRESS | INPUTS | OE | CE
Block Diagram | GND VPP | VCC DATA OUTPUTS | O0 - O15 | OE, CE AND PROGRAM LOGIC | Y DECODER | X DECODER | OUTPUT BUFFERS | Y-GATING | CELL MATRIX | IDENTIFICATION | A0 - A17 ADDRESS | INPUTS | OE | CE
P5 · p05_fig011836×883px
AT27C2048-15PC (PDIP-40) — Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
Notes: 1. Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
P5 · p05_fig02877×616px
AT27C2048-15PC (PDIP-40) — 5. Output float is defined as the point when data is no longer driven.
5. Output float is defined as the point when data is no longer driven.
P5 · p05_fig03819×516px
AT27C2048-15PC (PDIP-40) — 5. Output float is defined as the point when data is no longer driven.
5. Output float is defined as the point when data is no longer driven.
P5 · p05_fig04874×616px
AT27C2048-15PC (PDIP-40) — Symbol Typ Max Units Conditions
Symbol Typ Max Units Conditions
P5 · p05_fig03P5
AT27C2048-15PC (PDIP-40) — Datasheet Page 5 (p05_fig03)
Datasheet Page 5 (p05_fig03)
P10 · p10_fig012040×2566px
AT27C2048-15PC (PDIP-40) — AT27C2048 10 | Packaging Information | .045(1.14) X 45° PIN NO. 1 IDENTIFY | .045(1.14) X 30° - 45° .012(.305) .008(.203) | .021(.533) .013(.330) | .630(16.0) .590(15.0) | .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) |
AT27C2048 10 | Packaging Information | .045(1.14) X 45° PIN NO. 1 IDENTIFY | .045(1.14) X 30° - 45° .012(.305) .008(.203) | .021(.533) .013(.330) | .630(16.0) .590(15.0) | .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) |
P10 · p10_fig01P10
AT27C2048-15PC (PDIP-40) — Datasheet Page 10 (p10_fig01)
Datasheet Page 10 (p10_fig01)

Technical Specifications & Part Details (AT27C2048-15PC)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT27C2048-15PC (PDIP-40) is a 40-pin standard electronic & interconnect component featuring a 50.26 × 13.90 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -55°C to +125°C with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-55°C to +125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
5 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
10 µA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
50.26 × 13.90 × 4.20 mm (A1=0.51 mm)
Package family: DIP (PDIP-40)
Pin Count & Lead PitchN / e
40 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol40 auto-grouped pins
OK
IPC-7351B Land Pattern40 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-40)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
50.26 × 13.90 mm
Height (A) & Pitch (e)IPC-7351B
A=4.20mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
40P / 40Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PDIP-40
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT27C2048-15PC (PDIP-40)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT27C2048-15PC (PDIP-40)?

Manufactured by MICROCHIP, the AT27C2048-15PC is housed in a PDIP-40 package with 40 pins and a 2.54 mm lead pitch. Key pins include: 1 (DeviceType: Multiplexed I/O & Peripheral Pin DeviceType (General)), 2 (CE#: Multiplexed I/O & Peripheral Pin CE# (General)), 3 (O15: Multiplexed I/O & Peripheral Pin O15 (General)), 4 (O14: Multiplexed I/O & Peripheral Pin O14 (General)), 5 (O13: Multiplexed I/O & Peripheral Pin O13 (General)), 6 (O12: Multiplexed I/O & Peripheral Pin O12 (General)).

What are the IPC-7351B PCB Footprint dimensions for AT27C2048-15PC?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT27C2048-15PC (PDIP-40) has a nominal body envelope of 13.90 × 50.26 mm, pitch e = 2.54 mm, and 40 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT27C2048-15PC?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT27C2048-15PC (MICROCHIP, PDIP-40) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (40 pins) & AT27C2048 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DeviceTypeDigital_IOSignal terminal DeviceType (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DeviceType. Supported peripheral buses: General.
2CE#Digital_IOSignal terminal CE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CE#. Supported peripheral buses: General.
3O15Digital_IOSignal terminal O15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O15. Supported peripheral buses: General.
4O14Digital_IOSignal terminal O14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O14. Supported peripheral buses: General.
5O13Digital_IOSignal terminal O13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O13. Supported peripheral buses: General.
6O12Digital_IOSignal terminal O12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O12. Supported peripheral buses: General.
7O11Digital_IOSignal terminal O11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O11. Supported peripheral buses: General.
8O10Digital_IOSignal terminal O10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O10. Supported peripheral buses: General.
9O9Digital_IOSignal terminal O9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O9. Supported peripheral buses: General.
10O8Digital_IOSignal terminal O8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O8. Supported peripheral buses: General.
11GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
12O7Digital_IOSignal terminal O7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O7. Supported peripheral buses: General.
13O6Digital_IOSignal terminal O6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O6. Supported peripheral buses: General.
14O5Digital_IOSignal terminal O5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O5. Supported peripheral buses: General.
15O4Digital_IOSignal terminal O4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O4. Supported peripheral buses: General.
16O3Digital_IOSignal terminal O3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O3. Supported peripheral buses: General.
17O2Digital_IOSignal terminal O2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O2. Supported peripheral buses: General.
18O1Digital_IOSignal terminal O1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O1. Supported peripheral buses: General.
19O0Digital_IOSignal terminal O0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: O0. Supported peripheral buses: General.
20OE#Digital_IOSignal terminal OE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OE#. Supported peripheral buses: General.
21A0Digital_IOSignal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
22A1Digital_IOSignal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
23A2Digital_IOSignal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
24A3Digital_IOSignal terminal A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
25A4Digital_IOSignal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
26A5Digital_IOSignal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
27A6Digital_IOSignal terminal A6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6. Supported peripheral buses: General.
28A7Digital_IOSignal terminal A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7. Supported peripheral buses: General.
29A8Digital_IOSignal terminal A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A8. Supported peripheral buses: General.
30GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
31A9Digital_IOSignal terminal A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A9. Supported peripheral buses: General.
32A10Digital_IOSignal terminal A10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A10. Supported peripheral buses: General.
33A11Digital_IOSignal terminal A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A11. Supported peripheral buses: General.
34A12Digital_IOSignal terminal A12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A12. Supported peripheral buses: General.
35A13Digital_IOSignal terminal A13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A13. Supported peripheral buses: General.
36A14Digital_IOSignal terminal A14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A14. Supported peripheral buses: General.
37A15Digital_IOSignal terminal A15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A15. Supported peripheral buses: General.
38A16Digital_IOSignal terminal A16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A16. Supported peripheral buses: General.
39PGM#Digital_IOSignal terminal PGM# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PGM#. Supported peripheral buses: General.
40VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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