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SY100S301JC-TR (PLCC-28(11.5x11.5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

SY100S301JC-TR

MICROCHIPID: C19295198PLCC-28(11.5x11.5) · 28 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · SY100S301JC-TR (PLCC-28(11.5x11.5))1VCC2VCCA3Ob4Ob#5Oa#6Oa7D1a8VEES9D2a10D3a11D4a12D5a13D1b14VEE28VCC27Oc#26Oc25D5c24D4c23D3c22VEES21D2c20D1c19D5b18D4b17D3b16D2b15VEESGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
28272625242322212019181716151413121110987654321E=11.50mm · Pitch e=1.27mmD=11.50mm-10-8-6-4-202468101086420-2-4-6-8-10mm
3. 3D CAD MODEL
Package Body: 11.50mm × 11.50mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
2VCCAPowerPower Supply Input (VCCA — 3.3V / 5.0V Standard Logic)
3ObI/OMultiplexed I/O & Peripheral Pin Ob (General)
4Ob#I/OMultiplexed I/O & Peripheral Pin Ob# (General)
5Oa#I/OMultiplexed I/O & Peripheral Pin Oa# (General)
6OaI/OMultiplexed I/O & Peripheral Pin Oa (General)
7D1aI/OMultiplexed I/O & Peripheral Pin D1a (General)
8VEESI/OMultiplexed I/O & Peripheral Pin VEES (General)
9D2aI/OMultiplexed I/O & Peripheral Pin D2a (General)
10D3aI/OMultiplexed I/O & Peripheral Pin D3a (General)
11D4aI/OMultiplexed I/O & Peripheral Pin D4a (General)
12D5aI/OMultiplexed I/O & Peripheral Pin D5a (General)
13D1bI/OMultiplexed I/O & Peripheral Pin D1b (General)
14VEEI/OMultiplexed I/O & Peripheral Pin VEE (General)
15VEESI/OMultiplexed I/O & Peripheral Pin VEES (General)
16D2bI/OMultiplexed I/O & Peripheral Pin D2b (General)
17D3bI/OMultiplexed I/O & Peripheral Pin D3b (General)
18D4bI/OMultiplexed I/O & Peripheral Pin D4b (General)
19D5bI/OMultiplexed I/O & Peripheral Pin D5b (General)
20D1cI/OMultiplexed I/O & Peripheral Pin D1c (General)
21D2cI/OMultiplexed I/O & Peripheral Pin D2c (General)
22VEESI/OMultiplexed I/O & Peripheral Pin VEES (General)
23D3cI/OMultiplexed I/O & Peripheral Pin D3c (General)
24D4cI/OMultiplexed I/O & Peripheral Pin D4c (General)
25D5cI/OMultiplexed I/O & Peripheral Pin D5c (General)
26OcI/OMultiplexed I/O & Peripheral Pin Oc (General)
27Oc#I/OMultiplexed I/O & Peripheral Pin Oc# (General)
28VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
PIN 1 VCC
Power
Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: SY100S301JC-TR (MICROCHIP · PLCC-28(11.5x11.5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
SY100S301JC-TR (PLCC-28(11.5x11.5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
SY100S301JC-TR (PLCC-28(11.5x11.5)) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
SY100S301JC-TR (PLCC-28(11.5x11.5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SY100S301JC-TR (PLCC-28(11.5x11.5)) - 4. Package Dimensions (D×E×A)
PLCC-28(11.5x11.5) · 11.50×11.50mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
SY100S301JC-TR (PLCC-28(11.5x11.5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
SY100S301JC-TR (PLCC-28(11.5x11.5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for SY100
P5 · p05_fig01EXACT PACKAGE
SY100S301JC-TR (PLCC-28(11.5x11.5)) — 5 | SY100S301 Micrel, Inc. | M9999-042307 hbwhelp@micrel.com or (408) 955-1690 | 28-PIN PLCC (J28-1) | Rev. A | MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA | Micrel reserves the right to change circuitry and specifications at any
5 | SY100S301 Micrel, Inc. | M9999-042307 hbwhelp@micrel.com or (408) 955-1690 | 28-PIN PLCC (J28-1) | Rev. A | MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA | Micrel reserves the right to change circuitry and specifications at any
P1 · p01_fig012038×2810px
SY100S301JC-TR (PLCC-28(11.5x11.5)) — 1 | SY100S301 Micrel, Inc. | M9999-042307 hbwhelp@micrel.com or (408) 955-1690 | DESCRIPTION | The SY100S301 is an ultra-fast triple 5-input OR/NOR gate designed for use in high-performance ECL systems. The inputs on this device have 75kΩ p
1 | SY100S301 Micrel, Inc. | M9999-042307 hbwhelp@micrel.com or (408) 955-1690 | DESCRIPTION | The SY100S301 is an ultra-fast triple 5-input OR/NOR gate designed for use in high-performance ECL systems. The inputs on this device have 75kΩ p
P2 · p02_fig012041×2701px
SY100S301JC-TR (PLCC-28(11.5x11.5)) — 2 | SY100S301 Micrel, Inc. | M9999-042307 hbwhelp@micrel.com or (408) 955-1690 | PACKAGE/ORDERING INFORMATION | Ordering Information | Package Operating Package Lead Part Number Type Range Marking Finish | SY100S301JC J28-1 Commercial SY100
2 | SY100S301 Micrel, Inc. | M9999-042307 hbwhelp@micrel.com or (408) 955-1690 | PACKAGE/ORDERING INFORMATION | Ordering Information | Package Operating Package Lead Part Number Type Range Marking Finish | SY100S301JC J28-1 Commercial SY100
P3 · p03_fig012038×2701px
SY100S301JC-TR (PLCC-28(11.5x11.5)) — 3 | SY100S301 Micrel, Inc. | M9999-042307 hbwhelp@micrel.com or (408) 955-1690 | LOGIC EQUATION | Oa = D1a + D2a + D3a + D4a + D5a Ob = D1b + D2b + D3b + D4a + D5b Oc = D1c + D2c + D3c + D4c + D5c | DC ELECTRICAL CHARACTERISTICS | VEE = -4.
3 | SY100S301 Micrel, Inc. | M9999-042307 hbwhelp@micrel.com or (408) 955-1690 | LOGIC EQUATION | Oa = D1a + D2a + D3a + D4a + D5a Ob = D1b + D2b + D3b + D4a + D5b Oc = D1c + D2c + D3c + D4c + D5c | DC ELECTRICAL CHARACTERISTICS | VEE = -4.
P3 · p03_fig01P3
SY100S301JC-TR (PLCC-28(11.5x11.5)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P4 · p04_fig012038×2701px
SY100S301JC-TR (PLCC-28(11.5x11.5)) — 4 | SY100S301 Micrel, Inc. | M9999-042307 hbwhelp@micrel.com or (408) 955-1690 | TIMING DIAGRAM | 20% | 80% | OUTPUT | INPUT | 50% | tPLH tPHL | 50% | 20% | 80% 50% | tPHL tPLH | tTLH tTHL | TRUE | COMPLEMENT | 0.7 ± 0.1 ns 0.7 ± 0.1 ns | P
4 | SY100S301 Micrel, Inc. | M9999-042307 hbwhelp@micrel.com or (408) 955-1690 | TIMING DIAGRAM | 20% | 80% | OUTPUT | INPUT | 50% | tPLH tPHL | 50% | 20% | 80% 50% | tPHL tPLH | tTLH tTHL | TRUE | COMPLEMENT | 0.7 ± 0.1 ns 0.7 ± 0.1 ns | P

Technical Specifications & Part Details (SY100S301JC-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:SY100S301JC-TR (PLCC-28(11.5x11.5)) is a 28-pin standard electronic & interconnect component featuring a 11.50 × 11.50 × 1.15 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
11.50 × 11.50 × 1.15 mm (A1=0.03 mm)
Package family: LGA (PLCC-28(11.5x11.5))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PLCC-28(11.5x11.5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
11.50 × 11.50 mm
Height (A) & Pitch (e)IPC-7351B
A=1.15mm · e=1.27mm
Pad Size (W × L)Level B
0.76 × 2.03 mm
Pins / Total PadsTopology
28P / 28Pad (LGA_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PLCC-28(11.5x11.5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — SY100S301JC-TR (PLCC-28(11.5x11.5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of SY100S301JC-TR (PLCC-28(11.5x11.5))?

Manufactured by MICROCHIP, the SY100S301JC-TR is housed in a PLCC-28(11.5x11.5) package with 28 pins and a 1.27 mm lead pitch. Key pins include: 1 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 2 (VCCA: Power Supply Input (VCCA — 3.3V / 5.0V Standard Logic)), 3 (Ob: Multiplexed I/O & Peripheral Pin Ob (General)), 4 (Ob#: Multiplexed I/O & Peripheral Pin Ob# (General)), 5 (Oa#: Multiplexed I/O & Peripheral Pin Oa# (General)), 6 (Oa: Multiplexed I/O & Peripheral Pin Oa (General)).

What are the IPC-7351B PCB Footprint dimensions for SY100S301JC-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SY100S301JC-TR (PLCC-28(11.5x11.5)) has a nominal body envelope of 11.50 × 11.50 mm, pitch e = 1.27 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SY100S301JC-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SY100S301JC-TR (MICROCHIP, PLCC-28(11.5x11.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & SY100 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2VCCAPower_InPrimary positive power supply input (VCCA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3ObDigital_IOSignal terminal Ob (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Ob. Supported peripheral buses: General.
4Ob#Digital_IOSignal terminal Ob# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Ob#. Supported peripheral buses: General.
5Oa#Digital_IOSignal terminal Oa# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Oa#. Supported peripheral buses: General.
6OaDigital_IOSignal terminal Oa (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Oa. Supported peripheral buses: General.
7D1aDigital_IOSignal terminal D1a (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D1a. Supported peripheral buses: General.
8VEESDigital_IOSignal terminal VEES (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VEES. Supported peripheral buses: General.
9D2aDigital_IOSignal terminal D2a (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D2a. Supported peripheral buses: General.
10D3aDigital_IOSignal terminal D3a (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D3a. Supported peripheral buses: General.
11D4aDigital_IOSignal terminal D4a (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D4a. Supported peripheral buses: General.
12D5aDigital_IOSignal terminal D5a (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5a. Supported peripheral buses: General.
13D1bDigital_IOSignal terminal D1b (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D1b. Supported peripheral buses: General.
14VEEDigital_IOSignal terminal VEE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VEE. Supported peripheral buses: General.
15VEESDigital_IOSignal terminal VEES (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VEES. Supported peripheral buses: General.
16D2bDigital_IOSignal terminal D2b (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D2b. Supported peripheral buses: General.
17D3bDigital_IOSignal terminal D3b (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D3b. Supported peripheral buses: General.
18D4bDigital_IOSignal terminal D4b (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D4b. Supported peripheral buses: General.
19D5bDigital_IOSignal terminal D5b (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5b. Supported peripheral buses: General.
20D1cDigital_IOSignal terminal D1c (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D1c. Supported peripheral buses: General.
21D2cDigital_IOSignal terminal D2c (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D2c. Supported peripheral buses: General.
22VEESDigital_IOSignal terminal VEES (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VEES. Supported peripheral buses: General.
23D3cDigital_IOSignal terminal D3c (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D3c. Supported peripheral buses: General.
24D4cDigital_IOSignal terminal D4c (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D4c. Supported peripheral buses: General.
25D5cDigital_IOSignal terminal D5c (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5c. Supported peripheral buses: General.
26OcDigital_IOSignal terminal Oc (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Oc. Supported peripheral buses: General.
27Oc#Digital_IOSignal terminal Oc# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Oc#. Supported peripheral buses: General.
28VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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