CH32X033F8P6 (TSSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32X033F8P6

WCHID: C19268290TSSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32X033F8P6 (TSSOP-20)1IO12IO233V34PB7/RST/T1C25PC1 I/O/A PC6PA0 I/O/A PA7GND P GND8IO09V P VDD DD10PA4 I/O/A PA20IO919IO2018IO1917IO816IO1815IO1714IO1613IO1512PA6 I/O/A PA11IO6Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO1I/OGeneral Purpose Digital I/O Pin IO1
2IO2I/OGeneral Purpose Digital I/O Pin IO2
33V3Power3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4PB7/RST/T1C2N/O2P2I/OMultiplexed I/O & Peripheral Pin PB7/RST/T1C2N/O2P2 (General)
5PC1 I/O/A PC1I/OMultiplexed I/O & Peripheral Pin PC1 I/O/A PC1 (General)
6PA0 I/O/A PA0I/OMultiplexed I/O & Peripheral Pin PA0 I/O/A PA0 (UART)
7GND P GNDGNDGround Reference Pin (GND P GND)
8IO0I/OGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9V P VDD DDPowerPower Supply Input (V P VDD DD — 2V~5.5V)
10PA4 I/O/A PA4I/OMultiplexed I/O & Peripheral Pin PA4 I/O/A PA4 (UART)
11IO6I/OGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12PA6 I/O/A PA6I/OMultiplexed I/O & Peripheral Pin PA6 I/O/A PA6 (UART, SPI)
13IO15I/OGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14IO16I/OGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15IO17I/OGPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16IO18I/OGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17IO8I/OGPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1
18IO19I/OGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20I/OGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20IO9I/OGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
PIN 1 IO1
I/O
General Purpose Digital I/O Pin IO1
Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32X033F8P6 (WCH · TSSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32X033F8P6 (TSSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32X033F8P6 (TSSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32X033F8P6 (TSSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32X033F8P6 (TSSOP-20) - 4. Package Dimensions (D×E×A)
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32X033F8P6 (TSSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32X033F8P6 (TSSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH32X035 / CH32X033
P17 · p17_fig01EXACT PACKAGE
CH32X033F8P6 (TSSOP-20) — V2.2 15
V2.2 15
P18 · p18_fig01EXACT PACKAGE
CH32X033F8P6 (TSSOP-20) — V2.2 16
V2.2 16
P2 · p02_fig011815×850px
CH32X033F8P6 (TSSOP-20) — 型号 Code Flash RAM | 通 用 I/O | 高 级 定 时 器 | 通 用 定 时 | 器 | 串 口 | 看 门 狗 | PDUSB | ADC | OPA | 运 放 | CMP 比较 | 器 | 电容 触摸 按键 | SPI | PIOC 单线 接口 | 封装 形式 USB | 主 机 | USB | 设 备 | Type-C Source | Sink | DRP | CH32X035R8T6 62K 20K 60 2 1 4 2 √ √ √ 14+1
型号 Code Flash RAM | 通 用 I/O | 高 级 定 时 器 | 通 用 定 时 | 器 | 串 口 | 看 门 狗 | PDUSB | ADC | OPA | 运 放 | CMP 比较 | 器 | 电容 触摸 按键 | SPI | PIOC 单线 接口 | 封装 形式 USB | 主 机 | USB | 设 备 | Type-C Source | Sink | DRP | CH32X035R8T6 62K 20K 60 2 1 4 2 √ √ √ 14+1
P11 · p11_fig011874×1871px
CH32X033F8P6 (TSSOP-20) — 第2 章 引脚信息
第2 章 引脚信息
P11 · p11_fig01P11
CH32X033F8P6 (TSSOP-20) — Datasheet Page 11 (p11_fig01)
Datasheet Page 11 (p11_fig01)
P18 · p18_fig01P18
CH32X033F8P6 (TSSOP-20) — Datasheet Page 18 (p18_fig01)
Datasheet Page 18 (p18_fig01)

Technical Specifications & Part Details (CH32X033F8P6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH32X033F8P6 (TSSOP-20) is a 20-pin standard electronic & interconnect component featuring a 6.50 × 4.40 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2V~5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
2V~5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.00 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32X033F8P6 (TSSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32X033F8P6 (TSSOP-20)?

Manufactured by WCH, the CH32X033F8P6 is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2V~5.5V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (PB7/RST/T1C2N/O2P2: Multiplexed I/O & Peripheral Pin PB7/RST/T1C2N/O2P2 (General)), 5 (PC1 I/O/A PC1: Multiplexed I/O & Peripheral Pin PC1 I/O/A PC1 (General)), 6 (PA0 I/O/A PA0: Multiplexed I/O & Peripheral Pin PA0 I/O/A PA0 (UART)).

What are the IPC-7351B PCB Footprint dimensions for CH32X033F8P6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32X033F8P6 (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32X033F8P6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32X033F8P6 (WCH, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & CH32X035 / CH32X033 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO1Digital_IOGeneral Purpose Digital I/O Pin IO1
2IO2Digital_IOGeneral Purpose Digital I/O Pin IO2
33V3Power_In3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4PB7/RST/T1C2N/O2P2Digital_IOSignal terminal PB7/RST/T1C2N/O2P2 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PB7/RST/T1C2N/O2P2. Supported peripheral buses: General.
5PC1 I/O/A PC1Digital_IOSignal terminal PC1 I/O/A PC1 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PC1 I/O/A PC1. Supported peripheral buses: General.
6PA0 I/O/A PA0Digital_IOSignal terminal PA0 I/O/A PA0 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA0 I/O/A PA0. Supported peripheral buses: UART.
7GND P GNDGND0V electrical ground return terminal (GND P GND) for internal core logic, I/O drivers, and analog sub-blocks.
8IO0Digital_IOGPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin)
9V P VDD DDPower_InPrimary positive power supply input (V P VDD DD) operating in the 2V~5.5V domain (Max rating: 5.5V).
10PA4 I/O/A PA4Digital_IOSignal terminal PA4 I/O/A PA4 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA4 I/O/A PA4. Supported peripheral buses: UART.
11IO6Digital_IOGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12PA6 I/O/A PA6Digital_IOSignal terminal PA6 I/O/A PA6 (I/O, 2V~5.5V domain). Multiplexed alternate functions: PA6 I/O/A PA6. Supported peripheral buses: UART, SPI.
13IO15Digital_IOGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14IO16Digital_IOGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15IO17Digital_IOGPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6
16IO18Digital_IOGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17IO8Digital_IOGPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1
18IO19Digital_IOGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20Digital_IOGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20IO9Digital_IOGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD