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CH545L (LQFP-64(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH545L

WCHID: C19183926LQFP-64(7x7) · 64 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH545L (LQFP-64(7x7))1SCK/TXD1 /AI2P6.0/DM03P6.1/DP04P6.2/DM15P6.3/DP16P6.4/DM27P6.5/DP28P6.6/DM39P6.7/DP310P3.0/RXD11P4.512P4.413P3.1/TXD14P3.2/INT015P3.3/INT1/MS16P3.4/T0/MSDA17P3.5/T1/MOSI18P3.6/MISO119P3.7/SCK120P4.321P4.222P4.623P4.724VDD25GND/VSS26P7.0/XI/PWM127P7.1/XO/RST#28DCO29P4.130P4.031PWM532PWM464MISO/RXD1 /A63MOSI/PWM0 /A62SCS/AIN461AIN360INT0 /AIN2_59T2EX/CAP2/AI58T2/CAP1/AIN057V356GND/VSS55VDD54SCL0/AIN853SDA0/AIN952SCL1/RXD /AI51SDA1/TXD /AI50SCL2/AIN1249SDA2/AIN1348SCL347SDA346P5.0/DM/HM045P5.1/DP/HP044P5.2/HM1/ALE43P5.3/HP142P5.4/HM241P5.5/HP240P5.6/HM339P5.7/HP338P2.7/TXD137P2.6/RXD136P2.5/PWM0/T235IO3534P2.3/PWM233PWM3Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.245.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=7.00mm · Pitch e=0.40mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1SCK/TXD1 /AIN7_I/OMultiplexed I/O & Peripheral Pin SCK/TXD1 /AIN7_ (UART, SPI, ADC)
2P6.0/DM0I/OMultiplexed I/O & Peripheral Pin P6.0/DM0 (General)
3P6.1/DP0I/OMultiplexed I/O & Peripheral Pin P6.1/DP0 (General)
4P6.2/DM1I/OMultiplexed I/O & Peripheral Pin P6.2/DM1 (General)
5P6.3/DP1I/OMultiplexed I/O & Peripheral Pin P6.3/DP1 (General)
6P6.4/DM2I/OMultiplexed I/O & Peripheral Pin P6.4/DM2 (General)
7P6.5/DP2I/OMultiplexed I/O & Peripheral Pin P6.5/DP2 (General)
8P6.6/DM3I/OMultiplexed I/O & Peripheral Pin P6.6/DM3 (General)
9P6.7/DP3I/OMultiplexed I/O & Peripheral Pin P6.7/DP3 (General)
10P3.0/RXDI/OMultiplexed I/O & Peripheral Pin P3.0/RXD (UART)
11P4.5I/OMultiplexed I/O & Peripheral Pin P4.5 (General)
12P4.4I/OMultiplexed I/O & Peripheral Pin P4.4 (General)
13P3.1/TXDI/OMultiplexed I/O & Peripheral Pin P3.1/TXD (UART)
14P3.2/INT0I/OMultiplexed I/O & Peripheral Pin P3.2/INT0 (General)
15P3.3/INT1/MSCLI/OMultiplexed I/O & Peripheral Pin P3.3/INT1/MSCL (General)
16P3.4/T0/MSDAI/OMultiplexed I/O & Peripheral Pin P3.4/T0/MSDA (General)
17P3.5/T1/MOSI1I/OMultiplexed I/O & Peripheral Pin P3.5/T1/MOSI1 (SPI)
18P3.6/MISO1I/OMultiplexed I/O & Peripheral Pin P3.6/MISO1 (SPI)
19P3.7/SCK1I/OMultiplexed I/O & Peripheral Pin P3.7/SCK1 (SPI)
20P4.3I/OMultiplexed I/O & Peripheral Pin P4.3 (General)
21P4.2I/OMultiplexed I/O & Peripheral Pin P4.2 (General)
22P4.6I/OMultiplexed I/O & Peripheral Pin P4.6 (General)
23P4.7I/OMultiplexed I/O & Peripheral Pin P4.7 (General)
24VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
25GND/VSSGNDGround Reference Pin (GND/VSS)
26P7.0/XI/PWM1_I/OMultiplexed I/O & Peripheral Pin P7.0/XI/PWM1_ (PWM, RTC/CLK)
27P7.1/XO/RST#/ALE_I/OMultiplexed I/O & Peripheral Pin P7.1/XO/RST#/ALE_ (RTC/CLK)
28DCOI/OMultiplexed I/O & Peripheral Pin DCO (General)
29P4.1I/OMultiplexed I/O & Peripheral Pin P4.1 (General)
30P4.0I/OMultiplexed I/O & Peripheral Pin P4.0 (General)
31PWM5I/OMultiplexed I/O & Peripheral Pin PWM5 (PWM)
32PWM4I/OMultiplexed I/O & Peripheral Pin PWM4 (PWM)
33PWM3I/OMultiplexed I/O & Peripheral Pin PWM3 (PWM)
34P2.3/PWM2I/OMultiplexed I/O & Peripheral Pin P2.3/PWM2 (PWM)
35IO35I/OGeneral Purpose Digital I/O Pin IO35
36P2.5/PWM0/T2EX_/CAP2_I/OMultiplexed I/O & Peripheral Pin P2.5/PWM0/T2EX_/CAP2_ (PWM)
37P2.6/RXD1I/OMultiplexed I/O & Peripheral Pin P2.6/RXD1 (UART)
38P2.7/TXD1I/OMultiplexed I/O & Peripheral Pin P2.7/TXD1 (UART)
39P5.7/HP3I/OMultiplexed I/O & Peripheral Pin P5.7/HP3 (General)
40P5.6/HM3I/OMultiplexed I/O & Peripheral Pin P5.6/HM3 (General)
41P5.5/HP2I/OMultiplexed I/O & Peripheral Pin P5.5/HP2 (General)
42P5.4/HM2I/OMultiplexed I/O & Peripheral Pin P5.4/HM2 (General)
43P5.3/HP1I/OMultiplexed I/O & Peripheral Pin P5.3/HP1 (General)
44P5.2/HM1/ALEI/OMultiplexed I/O & Peripheral Pin P5.2/HM1/ALE (General)
45P5.1/DP/HP0I/OMultiplexed I/O & Peripheral Pin P5.1/DP/HP0 (General)
46P5.0/DM/HM0I/OMultiplexed I/O & Peripheral Pin P5.0/DM/HM0 (General)
47SDA3I/OMultiplexed I/O & Peripheral Pin SDA3 (I2C)
48SCL3I/OMultiplexed I/O & Peripheral Pin SCL3 (I2C)
49SDA2/AIN13I/OMultiplexed I/O & Peripheral Pin SDA2/AIN13 (I2C, ADC)
50SCL2/AIN12I/OMultiplexed I/O & Peripheral Pin SCL2/AIN12 (I2C, ADC)
51SDA1/TXD /AIN11_I/OMultiplexed I/O & Peripheral Pin SDA1/TXD /AIN11_ (UART, I2C, ADC)
52SCL1/RXD /AIN10_I/OMultiplexed I/O & Peripheral Pin SCL1/RXD /AIN10_ (UART, I2C, ADC)
53SDA0/AIN9I/OMultiplexed I/O & Peripheral Pin SDA0/AIN9 (I2C, ADC)
54SCL0/AIN8I/OMultiplexed I/O & Peripheral Pin SCL0/AIN8 (UART, I2C, ADC)
55VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
56GND/VSSGNDGround Reference Pin (GND/VSS)
57V3PowerRegulated Power Output (V3 — 3.3V / 5.0V Standard Logic)
58T2/CAP1/AIN0I/OMultiplexed I/O & Peripheral Pin T2/CAP1/AIN0 (SPI, ADC)
59T2EX/CAP2/AIN1I/OMultiplexed I/O & Peripheral Pin T2EX/CAP2/AIN1 (ADC)
60INT0 /AIN2_I/OMultiplexed I/O & Peripheral Pin INT0 /AIN2_ (ADC)
61AIN3I/OMultiplexed I/O & Peripheral Pin AIN3 (ADC)
62SCS/AIN4I/OMultiplexed I/O & Peripheral Pin SCS/AIN4 (ADC)
63MOSI/PWM0 /AIN5_I/OMultiplexed I/O & Peripheral Pin MOSI/PWM0 /AIN5_ (SPI, ADC, PWM)
64MISO/RXD1 /AIN6_I/OMultiplexed I/O & Peripheral Pin MISO/RXD1 /AIN6_ (UART, SPI, ADC)
PIN 1 SCK/TXD1 /AIN7_
I/O
Multiplexed I/O & Peripheral Pin SCK/TXD1 /AIN7_ (UART, SPI, ADC)
Design note: Signal terminal SCK/TXD1 /AIN7_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK/TXD1 /AIN7_. Supported peripheral buses: UART, SPI, ADC.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH545L (WCH · LQFP-64(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH545L (LQFP-64(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH545L (LQFP-64(7x7)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH545L (LQFP-64(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH545L (LQFP-64(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-64(7x7) · 7.00×7.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH545L (LQFP-64(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH545L (LQFP-64(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH545
P119 · p119_fig01EXACT PACKAGE
CH545L (LQFP-64(7x7)) — 20.1 LQFP48-7*7
20.1 LQFP48-7*7
P119 · p119_fig02EXACT PACKAGE
CH545L (LQFP-64(7x7)) — 20.2 LQFP64-7*7
20.2 LQFP64-7*7
P2 · p02_fig011736×913px
CH545L (LQFP-64(7x7)) — CH545 Datasheet 2 http://wch.cn
CH545 Datasheet 2 http://wch.cn
P2 · p02_fig021870×899px
CH545L (LQFP-64(7x7)) — MCU Internal Address & Data & DMA Bus | DP0/DM0 DP1/DM1 DP2/DM2 DP3/DM3 PassThrough UH0 UH1 UH2 UH3 USBX0 USBX1 USBX2 USBX3 USB/USB-host To 0# PC To 1# PC To 2# PC To 3# PC To PC or 0#/1#/2#/3# Device | Default USB Device | LS/FS | USB Engi
MCU Internal Address & Data & DMA Bus | DP0/DM0 DP1/DM1 DP2/DM2 DP3/DM3 PassThrough UH0 UH1 UH2 UH3 USBX0 USBX1 USBX2 USBX3 USB/USB-host To 0# PC To 1# PC To 2# PC To 3# PC To PC or 0#/1#/2#/3# Device | Default USB Device | LS/FS | USB Engi
P2 · p02_fig02P2
CH545L (LQFP-64(7x7)) — Datasheet Page 2 (p02_fig02)
Datasheet Page 2 (p02_fig02)

Technical Specifications & Part Details (CH545L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH545L (LQFP-64(7x7)) is a 64-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64(7x7))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-64(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.40mm
Pad Size (W × L)Level B
0.24 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-64(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH545L (LQFP-64(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH545L (LQFP-64(7x7))?

Manufactured by WCH, the CH545L is housed in a LQFP-64(7x7) package with 64 pins and a 0.40 mm lead pitch. Key pins include: 1 (SCK/TXD1 /AIN7_: Multiplexed I/O & Peripheral Pin SCK/TXD1 /AIN7_ (UART, SPI, ADC)), 2 (P6.0/DM0: Multiplexed I/O & Peripheral Pin P6.0/DM0 (General)), 3 (P6.1/DP0: Multiplexed I/O & Peripheral Pin P6.1/DP0 (General)), 4 (P6.2/DM1: Multiplexed I/O & Peripheral Pin P6.2/DM1 (General)), 5 (P6.3/DP1: Multiplexed I/O & Peripheral Pin P6.3/DP1 (General)), 6 (P6.4/DM2: Multiplexed I/O & Peripheral Pin P6.4/DM2 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH545L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH545L (LQFP-64(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.40 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH545L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH545L (WCH, LQFP-64(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & CH545 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1SCK/TXD1 /AIN7_Digital_IOSignal terminal SCK/TXD1 /AIN7_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK/TXD1 /AIN7_. Supported peripheral buses: UART, SPI, ADC.
2P6.0/DM0Digital_IOSignal terminal P6.0/DM0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P6.0/DM0. Supported peripheral buses: General.
3P6.1/DP0Digital_IOSignal terminal P6.1/DP0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P6.1/DP0. Supported peripheral buses: General.
4P6.2/DM1Digital_IOSignal terminal P6.2/DM1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P6.2/DM1. Supported peripheral buses: General.
5P6.3/DP1Digital_IOSignal terminal P6.3/DP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P6.3/DP1. Supported peripheral buses: General.
6P6.4/DM2Digital_IOSignal terminal P6.4/DM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P6.4/DM2. Supported peripheral buses: General.
7P6.5/DP2Digital_IOSignal terminal P6.5/DP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P6.5/DP2. Supported peripheral buses: General.
8P6.6/DM3Digital_IOSignal terminal P6.6/DM3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P6.6/DM3. Supported peripheral buses: General.
9P6.7/DP3Digital_IOSignal terminal P6.7/DP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P6.7/DP3. Supported peripheral buses: General.
10P3.0/RXDDigital_IOSignal terminal P3.0/RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.0/RXD. Supported peripheral buses: UART.
11P4.5Digital_IOSignal terminal P4.5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.5. Supported peripheral buses: General.
12P4.4Digital_IOSignal terminal P4.4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.4. Supported peripheral buses: General.
13P3.1/TXDDigital_IOSignal terminal P3.1/TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.1/TXD. Supported peripheral buses: UART.
14P3.2/INT0Digital_IOSignal terminal P3.2/INT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.2/INT0. Supported peripheral buses: General.
15P3.3/INT1/MSCLDigital_IOSignal terminal P3.3/INT1/MSCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.3/INT1/MSCL. Supported peripheral buses: General.
16P3.4/T0/MSDADigital_IOSignal terminal P3.4/T0/MSDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.4/T0/MSDA. Supported peripheral buses: General.
17P3.5/T1/MOSI1Digital_IOSignal terminal P3.5/T1/MOSI1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.5/T1/MOSI1. Supported peripheral buses: SPI.
18P3.6/MISO1Digital_IOSignal terminal P3.6/MISO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.6/MISO1. Supported peripheral buses: SPI.
19P3.7/SCK1Digital_IOSignal terminal P3.7/SCK1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.7/SCK1. Supported peripheral buses: SPI.
20P4.3Digital_IOSignal terminal P4.3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.3. Supported peripheral buses: General.
21P4.2Digital_IOSignal terminal P4.2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.2. Supported peripheral buses: General.
22P4.6Digital_IOSignal terminal P4.6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.6. Supported peripheral buses: General.
23P4.7Digital_IOSignal terminal P4.7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.7. Supported peripheral buses: General.
24VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
25GND/VSSGND0V electrical ground return terminal (GND/VSS) for internal core logic, I/O drivers, and analog sub-blocks.
26P7.0/XI/PWM1_Digital_IOSignal terminal P7.0/XI/PWM1_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P7.0/XI/PWM1_. Supported peripheral buses: PWM, RTC/CLK.
27P7.1/XO/RST#/ALE_Digital_IOSignal terminal P7.1/XO/RST#/ALE_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P7.1/XO/RST#/ALE_. Supported peripheral buses: RTC/CLK.
28DCODigital_IOSignal terminal DCO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCO. Supported peripheral buses: General.
29P4.1Digital_IOSignal terminal P4.1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.1. Supported peripheral buses: General.
30P4.0Digital_IOSignal terminal P4.0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P4.0. Supported peripheral buses: General.
31PWM5Digital_IOSignal terminal PWM5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM5. Supported peripheral buses: PWM.
32PWM4Digital_IOSignal terminal PWM4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM4. Supported peripheral buses: PWM.
33PWM3Digital_IOSignal terminal PWM3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PWM3. Supported peripheral buses: PWM.
34P2.3/PWM2Digital_IOSignal terminal P2.3/PWM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.3/PWM2. Supported peripheral buses: PWM.
35IO35Digital_IOGeneral Purpose Digital I/O Pin IO35
36P2.5/PWM0/T2EX_/CAP2_Digital_IOSignal terminal P2.5/PWM0/T2EX_/CAP2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.5/PWM0/T2EX_/CAP2_. Supported peripheral buses: PWM.
37P2.6/RXD1Digital_IOSignal terminal P2.6/RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.6/RXD1. Supported peripheral buses: UART.
38P2.7/TXD1Digital_IOSignal terminal P2.7/TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.7/TXD1. Supported peripheral buses: UART.
39P5.7/HP3Digital_IOSignal terminal P5.7/HP3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.7/HP3. Supported peripheral buses: General.
40P5.6/HM3Digital_IOSignal terminal P5.6/HM3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.6/HM3. Supported peripheral buses: General.
41P5.5/HP2Digital_IOSignal terminal P5.5/HP2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.5/HP2. Supported peripheral buses: General.
42P5.4/HM2Digital_IOSignal terminal P5.4/HM2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.4/HM2. Supported peripheral buses: General.
43P5.3/HP1Digital_IOSignal terminal P5.3/HP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.3/HP1. Supported peripheral buses: General.
44P5.2/HM1/ALEDigital_IOSignal terminal P5.2/HM1/ALE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.2/HM1/ALE. Supported peripheral buses: General.
45P5.1/DP/HP0Digital_IOSignal terminal P5.1/DP/HP0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.1/DP/HP0. Supported peripheral buses: General.
46P5.0/DM/HM0Digital_IOSignal terminal P5.0/DM/HM0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.0/DM/HM0. Supported peripheral buses: General.
47SDA3Digital_IOSignal terminal SDA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA3. Supported peripheral buses: I2C.
48SCL3Digital_IOSignal terminal SCL3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL3. Supported peripheral buses: I2C.
49SDA2/AIN13Digital_IOSignal terminal SDA2/AIN13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA2/AIN13. Supported peripheral buses: I2C, ADC.
50SCL2/AIN12Digital_IOSignal terminal SCL2/AIN12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL2/AIN12. Supported peripheral buses: I2C, ADC.
51SDA1/TXD /AIN11_Digital_IOSignal terminal SDA1/TXD /AIN11_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA1/TXD /AIN11_. Supported peripheral buses: UART, I2C, ADC.
52SCL1/RXD /AIN10_Digital_IOSignal terminal SCL1/RXD /AIN10_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL1/RXD /AIN10_. Supported peripheral buses: UART, I2C, ADC.
53SDA0/AIN9Digital_IOSignal terminal SDA0/AIN9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA0/AIN9. Supported peripheral buses: I2C, ADC.
54SCL0/AIN8Digital_IOSignal terminal SCL0/AIN8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL0/AIN8. Supported peripheral buses: UART, I2C, ADC.
55VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
56GND/VSSGND0V electrical ground return terminal (GND/VSS) for internal core logic, I/O drivers, and analog sub-blocks.
57V3Power_OutRegulated power output rail (V3) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
58T2/CAP1/AIN0AnalogSignal terminal T2/CAP1/AIN0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI0. Supported peripheral buses: SPI, ADC.
59T2EX/CAP2/AIN1AnalogSignal terminal T2EX/CAP2/AIN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: T2EX/CAP2/AIN1. Supported peripheral buses: ADC.
60INT0 /AIN2_AnalogSignal terminal INT0 /AIN2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT0 /AIN2_. Supported peripheral buses: ADC.
61AIN3AnalogSignal terminal AIN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AIN3. Supported peripheral buses: ADC.
62SCS/AIN4AnalogSignal terminal SCS/AIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS/AIN4. Supported peripheral buses: ADC.
63MOSI/PWM0 /AIN5_Digital_IOSignal terminal MOSI/PWM0 /AIN5_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MOSI/PWM0 /AIN5_. Supported peripheral buses: SPI, ADC, PWM.
64MISO/RXD1 /AIN6_Digital_IOSignal terminal MISO/RXD1 /AIN6_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MISO/RXD1 /AIN6_. Supported peripheral buses: UART, SPI, ADC.
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