![CH368L (LQFP-100(14x14)) — 2、特点 | SPI/IIC | ADDR | WR# CS# | RD# | INT# | MEM_WR MEM_RD IOP_WR IOP_RD | D[31-0] | A[15-0] PCIE 信号 | CH368 接口芯片 | PCIE 总线 | RSTO | 配置接口 辅助接口 | CPU MCU 单片机 | 本地 32 位 被动 并行 接口 | 本地 32 位 或8 位 | 主动 并行 总线](/api/v1/assets/C191328/extracted/figures/p01_fig01.png)
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LQFP-100(14x14) · 100P
Synchronized Pinout (Symbol / 2D / 3D) (100/100)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | RSTO | I/O | Multiplexed I/O & Peripheral Pin RSTO (General) |
| 2 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 3 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 4 | RSVD | I/O | Multiplexed I/O & Peripheral Pin RSVD (General) |
| 5 | WAKE# | I/O | Multiplexed I/O & Peripheral Pin WAKE# (General) |
| 6 | PERST# | I/O | Multiplexed I/O & Peripheral Pin PERST# (General) |
| 7 | PERST# | I/O | Multiplexed I/O & Peripheral Pin PERST# (General) |
| 8 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 9 | GND | GND | Ground Reference Pin (GND) |
| 10 | VCC18 | Power | Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic) |
| 11 | PECKP | I/O | Multiplexed I/O & Peripheral Pin PECKP (General) |
| 12 | PECKN | I/O | Multiplexed I/O & Peripheral Pin PECKN (General) |
| 13 | VCC18A | Power | Power Supply Input (VCC18A — 3.3V / 5.0V Standard Logic) |
| 14 | GND | GND | Ground Reference Pin (GND) |
| 15 | GND | GND | Ground Reference Pin (GND) |
| 16 | RREF | I/O | Multiplexed I/O & Peripheral Pin RREF (General) |
| 17 | GND | GND | Ground Reference Pin (GND) |
| 18 | PERP | I/O | Multiplexed I/O & Peripheral Pin PERP (General) |
| 19 | PERN | I/O | Multiplexed I/O & Peripheral Pin PERN (General) |
| 20 | VCC18A | Power | Power Supply Input (VCC18A — 3.3V / 5.0V Standard Logic) |
| 21 | PETN | I/O | Multiplexed I/O & Peripheral Pin PETN (General) |
| 22 | PETP | I/O | Multiplexed I/O & Peripheral Pin PETP (General) |
| 23 | GND | GND | Ground Reference Pin (GND) |
| 24 | NC | I/O | Multiplexed I/O & Peripheral Pin NC (General) |
| 25 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 26 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 27 | GND | GND | Ground Reference Pin (GND) |
| 28 | SCL | I/O | Multiplexed I/O & Peripheral Pin SCL (SPI, I2C) |
| 29 | SDA | I/O | Multiplexed I/O & Peripheral Pin SDA (I2C) |
| 30 | SDX | I/O | Multiplexed I/O & Peripheral Pin SDX (SPI) |
| 31 | SCS | I/O | Multiplexed I/O & Peripheral Pin SCS (SPI) |
| 32 | INT# | I/O | Multiplexed I/O & Peripheral Pin INT# (General) |
| 33 | D31 | I/O | Multiplexed I/O & Peripheral Pin D31 (General) |
| 34 | D30 | I/O | Multiplexed I/O & Peripheral Pin D30 (General) |
| 35 | D29 | I/O | Multiplexed I/O & Peripheral Pin D29 (General) |
| 36 | D28 | I/O | Multiplexed I/O & Peripheral Pin D28 (General) |
| 37 | GND | GND | Ground Reference Pin (GND) |
| 38 | D27 | I/O | Multiplexed I/O & Peripheral Pin D27 (General) |
| 39 | D26 | I/O | Multiplexed I/O & Peripheral Pin D26 (General) |
| 40 | D25 | I/O | Multiplexed I/O & Peripheral Pin D25 (General) |
| 41 | D24 | I/O | Multiplexed I/O & Peripheral Pin D24 (General) |
| 42 | D23 | I/O | Multiplexed I/O & Peripheral Pin D23 (General) |
| 43 | D22 | I/O | Multiplexed I/O & Peripheral Pin D22 (General) |
| 44 | D21 | I/O | Multiplexed I/O & Peripheral Pin D21 (General) |
| 45 | D20 | I/O | Multiplexed I/O & Peripheral Pin D20 (General) |
| 46 | D19 | I/O | Multiplexed I/O & Peripheral Pin D19 (General) |
| 47 | D18 | I/O | Multiplexed I/O & Peripheral Pin D18 (General) |
| 48 | VCC18 | Power | Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic) |
| 49 | GND | GND | Exposed Thermal & Ground Pad (GND) |
| 50 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 51 | D17 | I/O | Multiplexed I/O & Peripheral Pin D17 (General) |
| 52 | D16 | I/O | Multiplexed I/O & Peripheral Pin D16 (General) |
| 53 | D15 | I/O | Multiplexed I/O & Peripheral Pin D15 (General) |
| 54 | D14 | I/O | Multiplexed I/O & Peripheral Pin D14 (General) |
| 55 | D13 | I/O | Multiplexed I/O & Peripheral Pin D13 (General) |
| 56 | D12 | I/O | Multiplexed I/O & Peripheral Pin D12 (General) |
| 57 | D11 | I/O | Multiplexed I/O & Peripheral Pin D11 (General) |
| 58 | D10 | I/O | Multiplexed I/O & Peripheral Pin D10 (General) |
| 59 | D9 | I/O | Multiplexed I/O & Peripheral Pin D9 (General) |
| 60 | D8 | I/O | Multiplexed I/O & Peripheral Pin D8 (General) |
| 61 | GND | GND | Ground Reference Pin (GND) |
| 62 | D7 | I/O | Multiplexed I/O & Peripheral Pin D7 (General) |
| 63 | D6 | I/O | Multiplexed I/O & Peripheral Pin D6 (General) |
| 64 | D5 | I/O | Multiplexed I/O & Peripheral Pin D5 (General) |
| 65 | D4 | I/O | Multiplexed I/O & Peripheral Pin D4 (General) |
| 66 | D3 | I/O | Multiplexed I/O & Peripheral Pin D3 (General) |
| 67 | D2 | I/O | Multiplexed I/O & Peripheral Pin D2 (General) |
| 68 | D1 | I/O | Multiplexed I/O & Peripheral Pin D1 (General) |
| 69 | D0 | I/O | Multiplexed I/O & Peripheral Pin D0 (General) |
| 70 | VCC18 | Power | Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic) |
| 71 | GND | GND | Ground Reference Pin (GND) |
| 72 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 73 | MEM_WR | I/O | Multiplexed I/O & Peripheral Pin MEM_WR (General) |
| 74 | MEM_RD | I/O | Multiplexed I/O & Peripheral Pin MEM_RD (General) |
| 75 | IOP_WR | I/O | Multiplexed I/O & Peripheral Pin IOP_WR (General) |
| 76 | IOP_RD | I/O | Multiplexed I/O & Peripheral Pin IOP_RD (General) |
| 77 | GND | GND | Ground Reference Pin (GND) |
| 78 | A0 | I/O | Multiplexed I/O & Peripheral Pin A0 (General) |
| 79 | A1 | I/O | Multiplexed I/O & Peripheral Pin A1 (General) |
| 80 | A2 | I/O | Multiplexed I/O & Peripheral Pin A2 (General) |
| 81 | A3 | I/O | Multiplexed I/O & Peripheral Pin A3 (General) |
| 82 | A4 | I/O | Multiplexed I/O & Peripheral Pin A4 (General) |
| 83 | A5 | I/O | Multiplexed I/O & Peripheral Pin A5 (General) |
| 84 | A6 | I/O | Multiplexed I/O & Peripheral Pin A6 (General) |
| 85 | A7 | I/O | Multiplexed I/O & Peripheral Pin A7 (General) |
| 86 | GND | GND | Ground Reference Pin (GND) |
| 87 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 88 | A8 | I/O | Multiplexed I/O & Peripheral Pin A8 (General) |
| 89 | A9 | I/O | Multiplexed I/O & Peripheral Pin A9 (General) |
| 90 | A10 | I/O | Multiplexed I/O & Peripheral Pin A10 (General) |
| 91 | A11 | I/O | Multiplexed I/O & Peripheral Pin A11 (General) |
| 92 | A12 | I/O | Multiplexed I/O & Peripheral Pin A12 (General) |
| 93 | A13 | I/O | Multiplexed I/O & Peripheral Pin A13 (General) |
| 94 | A14 | I/O | Multiplexed I/O & Peripheral Pin A14 (General) |
| 95 | A15 | I/O | Multiplexed I/O & Peripheral Pin A15 (General) |
| 96 | GND | GND | Ground Reference Pin (GND) |
| 97 | CS# | I/O | Multiplexed I/O & Peripheral Pin CS# (General) |
| 98 | ADDR | I/O | Multiplexed I/O & Peripheral Pin ADDR (SPI) |
| 99 | RD# | I/O | Multiplexed I/O & Peripheral Pin RD# (General) |
| 100 | WR# | I/O | Multiplexed I/O & Peripheral Pin WR# (General) |
PIN 1 RSTO
I/OMultiplexed I/O & Peripheral Pin RSTO (General)
Design note: 低电平有效的复位输出 通用输出 ，
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CH368
P2 · p02_fig01EXACT PACKAGE
P1 · p01_fig011550×1332px
P2 · p02_fig01P2
P11 · p11_fig011544×971px
P12 · p12_fig011626×2127px
P13 · p13_fig01526×223px
Technical Specifications & Part Details (CH368L)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH368L (LQFP-100(14x14)) is a 100-pin standard electronic & interconnect component featuring a 14.00 × 14.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
105
MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-100(14x14))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol100 auto-grouped pins
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH368 (2)
LQFP-100(14x14) · 100P
Mechanical Dimensions & Land Pattern (LQFP-100(14x14))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-100(14x14) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH368L (LQFP-100(14x14))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH368L (LQFP-100(14x14))?
Manufactured by WCH, the CH368L is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch. Key pins include: 1 (RSTO: Multiplexed I/O & Peripheral Pin RSTO (General)), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (RSVD: Multiplexed I/O & Peripheral Pin RSVD (General)), 5 (WAKE#: Multiplexed I/O & Peripheral Pin WAKE# (General)), 6 (PERST#: Multiplexed I/O & Peripheral Pin PERST# (General)).
What are the IPC-7351B PCB Footprint dimensions for CH368L?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH368L (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH368L?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH368L (WCH, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (100 pins) & CH368 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | RSTO | Digital_IO | Signal terminal RSTO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTO. Supported peripheral buses: General. |
| 2 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 3 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 4 | RSVD | NC | Signal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General. |
| 5 | WAKE# | Digital_IO | Signal terminal WAKE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WAKE#. Supported peripheral buses: General. |
| 6 | PERST# | Digital_IO | Signal terminal PERST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERST#. Supported peripheral buses: General. |
| 7 | PERST# | Digital_IO | Signal terminal PERST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERST#. Supported peripheral buses: General. |
| 8 | VCC33 | Power_In | Primary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 9 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 10 | VCC18 | Power_In | Primary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 11 | PECKP | Digital_IO | Signal terminal PECKP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PECKP. Supported peripheral buses: General. |
| 12 | PECKN | Digital_IO | Signal terminal PECKN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PECKN. Supported peripheral buses: General. |
| 13 | VCC18A | Power_In | Primary positive power supply input (VCC18A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 14 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 15 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 16 | RREF | Digital_IO | Signal terminal RREF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RREF. Supported peripheral buses: General. |
| 17 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 18 | PERP | Digital_IO | Signal terminal PERP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERP. Supported peripheral buses: General. |
| 19 | PERN | Digital_IO | Signal terminal PERN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERN. Supported peripheral buses: General. |
| 20 | VCC18A | Power_In | Primary positive power supply input (VCC18A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 21 | PETN | Digital_IO | Signal terminal PETN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PETN. Supported peripheral buses: General. |
| 22 | PETP | Digital_IO | Signal terminal PETP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PETP. Supported peripheral buses: General. |
| 23 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 24 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 25 | VCC33 | Power_In | Primary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 26 | VCC33 | Power_In | Primary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 27 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 28 | SCL | Digital_IO | Signal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: SPI, I2C. |
| 29 | SDA | Digital_IO | Signal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C. |
| 30 | SDX | Digital_IO | Signal terminal SDX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDX. Supported peripheral buses: SPI. |
| 31 | SCS | Digital_IO | Signal terminal SCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS. Supported peripheral buses: SPI. |
| 32 | INT# | Digital_IO | Signal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General. |
| 33 | D31 | Digital_IO | Signal terminal D31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D31. Supported peripheral buses: General. |
| 34 | D30 | Digital_IO | Signal terminal D30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D30. Supported peripheral buses: General. |
| 35 | D29 | Digital_IO | Signal terminal D29 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D29. Supported peripheral buses: General. |
| 36 | D28 | Digital_IO | Signal terminal D28 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D28. Supported peripheral buses: General. |
| 37 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 38 | D27 | Digital_IO | Signal terminal D27 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D27. Supported peripheral buses: General. |
| 39 | D26 | Digital_IO | Signal terminal D26 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D26. Supported peripheral buses: General. |
| 40 | D25 | Digital_IO | Signal terminal D25 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D25. Supported peripheral buses: General. |
| 41 | D24 | Digital_IO | Signal terminal D24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D24. Supported peripheral buses: General. |
| 42 | D23 | Digital_IO | Signal terminal D23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D23. Supported peripheral buses: General. |
| 43 | D22 | Digital_IO | Signal terminal D22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D22. Supported peripheral buses: General. |
| 44 | D21 | Digital_IO | Signal terminal D21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D21. Supported peripheral buses: General. |
| 45 | D20 | Digital_IO | Signal terminal D20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D20. Supported peripheral buses: General. |
| 46 | D19 | Digital_IO | Signal terminal D19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D19. Supported peripheral buses: General. |
| 47 | D18 | Digital_IO | Signal terminal D18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D18. Supported peripheral buses: General. |
| 48 | VCC18 | Power_In | Primary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 49 | GND | GND | Bottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |
| 50 | VCC33 | Power_In | Primary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 51 | D17 | Digital_IO | Signal terminal D17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D17. Supported peripheral buses: General. |
| 52 | D16 | Digital_IO | Signal terminal D16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D16. Supported peripheral buses: General. |
| 53 | D15 | Digital_IO | Signal terminal D15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D15. Supported peripheral buses: General. |
| 54 | D14 | Digital_IO | Signal terminal D14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D14. Supported peripheral buses: General. |
| 55 | D13 | Digital_IO | Signal terminal D13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D13. Supported peripheral buses: General. |
| 56 | D12 | Digital_IO | Signal terminal D12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D12. Supported peripheral buses: General. |
| 57 | D11 | Digital_IO | Signal terminal D11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D11. Supported peripheral buses: General. |
| 58 | D10 | Digital_IO | Signal terminal D10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D10. Supported peripheral buses: General. |
| 59 | D9 | Digital_IO | Signal terminal D9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D9. Supported peripheral buses: General. |
| 60 | D8 | Digital_IO | Signal terminal D8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D8. Supported peripheral buses: General. |
| 61 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 62 | D7 | Digital_IO | Signal terminal D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D7. Supported peripheral buses: General. |
| 63 | D6 | Digital_IO | Signal terminal D6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D6. Supported peripheral buses: General. |
| 64 | D5 | Digital_IO | Signal terminal D5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5. Supported peripheral buses: General. |