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CH367L (LQFP-64(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH367L

WCHID: C190823LQFP-64(7x7) · 64 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH367L (LQFP-64(7x7))1RSVD2WAKE#3PERST#4GND5VCC186PECKP/PECKN7PECKP/PECKN8VCC18A9GND10GND11RREF12PERP/PERN13PERP/PERN14VCC18A15PETP/PETN16PETP/PETN17GND18VCC3319GND20SCL21SDA22SDX23SCS24INT#25NC26NC27NC28NC29VCC1830GND31VCC3332GPI264RSTO63FIXID#62WAKIN#61SDI60GND59VCC3358GPO57GPO156GPO055A754A653A552A451A350A249A148A047VCC3346GND45IORD44IOWR43GND42VCC1841D040D139D238D337D436D535D634D733GPI1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.245.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=7.00mm · Pitch e=0.40mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
2WAKE#I/OMultiplexed I/O & Peripheral Pin WAKE# (General)
3PERST#I/OMultiplexed I/O & Peripheral Pin PERST# (General)
4GNDGNDGround Reference Pin (GND)
5VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
6PECKP/PECKNI/OMultiplexed I/O & Peripheral Pin PECKP/PECKN (General)
7PECKP/PECKNI/OMultiplexed I/O & Peripheral Pin PECKP/PECKN (General)
8VCC18APowerPower Supply Input (VCC18A — 3.3V / 5.0V Standard Logic)
9GNDGNDGround Reference Pin (GND)
10GNDGNDGround Reference Pin (GND)
11RREFI/OMultiplexed I/O & Peripheral Pin RREF (General)
12PERP/PERNI/OMultiplexed I/O & Peripheral Pin PERP/PERN (General)
13PERP/PERNI/OMultiplexed I/O & Peripheral Pin PERP/PERN (General)
14VCC18APowerPower Supply Input (VCC18A — 3.3V / 5.0V Standard Logic)
15PETP/PETNI/OMultiplexed I/O & Peripheral Pin PETP/PETN (General)
16PETP/PETNI/OMultiplexed I/O & Peripheral Pin PETP/PETN (General)
17GNDGNDGround Reference Pin (GND)
18VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
19GNDGNDGround Reference Pin (GND)
20SCLI/OMultiplexed I/O & Peripheral Pin SCL (SPI, I2C)
21SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
22SDXI/OMultiplexed I/O & Peripheral Pin SDX (SPI)
23SCSI/OMultiplexed I/O & Peripheral Pin SCS (SPI)
24INT#I/OMultiplexed I/O & Peripheral Pin INT# (General)
25NCI/OMultiplexed I/O & Peripheral Pin NC (General)
26NCI/OMultiplexed I/O & Peripheral Pin NC (General)
27NCI/OMultiplexed I/O & Peripheral Pin NC (General)
28NCI/OMultiplexed I/O & Peripheral Pin NC (General)
29VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
30GNDGNDGround Reference Pin (GND)
31VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
32GPI2I/OMultiplexed I/O & Peripheral Pin GPI2 (General)
33GPI1I/OMultiplexed I/O & Peripheral Pin GPI1 (General)
34D7I/OMultiplexed I/O & Peripheral Pin D7 (General)
35D6I/OMultiplexed I/O & Peripheral Pin D6 (General)
36D5I/OMultiplexed I/O & Peripheral Pin D5 (General)
37D4I/OMultiplexed I/O & Peripheral Pin D4 (General)
38D3I/OMultiplexed I/O & Peripheral Pin D3 (General)
39D2I/OMultiplexed I/O & Peripheral Pin D2 (General)
40D1I/OMultiplexed I/O & Peripheral Pin D1 (General)
41D0I/OMultiplexed I/O & Peripheral Pin D0 (General)
42VCC18PowerPower Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)
43GNDGNDGround Reference Pin (GND)
44IOWRI/OMultiplexed I/O & Peripheral Pin IOWR (General)
45IORDI/OMultiplexed I/O & Peripheral Pin IORD (General)
46GNDGNDGround Reference Pin (GND)
47VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
48A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
49A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
50A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
51A3I/OMultiplexed I/O & Peripheral Pin A3 (General)
52A4I/OMultiplexed I/O & Peripheral Pin A4 (General)
53A5I/OMultiplexed I/O & Peripheral Pin A5 (General)
54A6I/OMultiplexed I/O & Peripheral Pin A6 (General)
55A7I/OMultiplexed I/O & Peripheral Pin A7 (General)
56GPO0I/OMultiplexed I/O & Peripheral Pin GPO0 (General)
57GPO1I/OMultiplexed I/O & Peripheral Pin GPO1 (General)
58GPOI/OMultiplexed I/O & Peripheral Pin GPO (General)
59VCC33PowerPower Supply Input (VCC33 — 3.3V / 5.0V Standard Logic)
60GNDGNDGround Reference Pin (GND)
61SDII/OMultiplexed I/O & Peripheral Pin SDI (SPI)
62WAKIN#I/OMultiplexed I/O & Peripheral Pin WAKIN# (General)
63FIXID#I/OMultiplexed I/O & Peripheral Pin FIXID# (General)
64RSTOI/OMultiplexed I/O & Peripheral Pin RSTO (General)
PIN 1 RSVD
I/O
Multiplexed I/O & Peripheral Pin RSVD (General)
Design note: 保留引脚 禁止连接 ，
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH367L (WCH · LQFP-64(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH367L (LQFP-64(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH367L (LQFP-64(7x7)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH367L (LQFP-64(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH367L (LQFP-64(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-64(7x7) · 7.00×7.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH367L (LQFP-64(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH367L (LQFP-64(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH367
P2 · p02_fig02EXACT PACKAGE
CH367L (LQFP-64(7x7)) — 封装形式 塑体宽度 引脚间距 封装说明 订货型号
封装形式 塑体宽度 引脚间距 封装说明 订货型号
P1 · p01_fig011323×991px
CH367L (LQFP-64(7x7)) — 2、特点
2、特点
P2 · p02_fig01796×796px
CH367L (LQFP-64(7x7)) — 封装形式 塑体宽度 引脚间距 封装说明 订货型号
封装形式 塑体宽度 引脚间距 封装说明 订货型号
P2 · p02_fig01P2
CH367L (LQFP-64(7x7)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P9 · p09_fig011469×884px
CH367L (LQFP-64(7x7)) — 名称 参数说明 最小值 典型值 最大值 单位 FCLK CLK 输入频率（PCIE 总线的主频） 0 100 105 MHz FSCL2 两线接口自动加载时SCL 输出频率 244 260 KHz FSCL3 三线接口自动加载时SCL 输出频率 31 35 MHz TINTEG 有效边沿中断的最小脉冲宽度 5 nS
名称 参数说明 最小值 典型值 最大值 单位 FCLK CLK 输入频率（PCIE 总线的主频） 0 100 105 MHz FSCL2 两线接口自动加载时SCL 输出频率 244 260 KHz FSCL3 三线接口自动加载时SCL 输出频率 31 35 MHz TINTEG 有效边沿中断的最小脉冲宽度 5 nS
P9 · p09_fig01P9
CH367L (LQFP-64(7x7)) — Datasheet Page 9 (p09_fig01)
Datasheet Page 9 (p09_fig01)
P10 · p10_fig011344×1280px
CH367L (LQFP-64(7x7)) — 8.2. 连接配置芯片（下图）
8.2. 连接配置芯片（下图）
P10 · p10_fig02526×223px
CH367L (LQFP-64(7x7)) — 8.3. I/O 端口应用（下图）
8.3. I/O 端口应用（下图）

Technical Specifications & Part Details (CH367L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH367L (LQFP-64(7x7)) is a 64-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64(7x7))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-64(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.40mm
Pad Size (W × L)Level B
0.24 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-64(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH367L (LQFP-64(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH367L (LQFP-64(7x7))?

Manufactured by WCH, the CH367L is housed in a LQFP-64(7x7) package with 64 pins and a 0.40 mm lead pitch. Key pins include: 1 (RSVD: Multiplexed I/O & Peripheral Pin RSVD (General)), 2 (WAKE#: Multiplexed I/O & Peripheral Pin WAKE# (General)), 3 (PERST#: Multiplexed I/O & Peripheral Pin PERST# (General)), 4 (GND: Ground Reference Pin (GND)), 5 (VCC18: Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic)), 6 (PECKP/PECKN: Multiplexed I/O & Peripheral Pin PECKP/PECKN (General)).

What are the IPC-7351B PCB Footprint dimensions for CH367L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH367L (LQFP-64(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.40 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH367L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH367L (WCH, LQFP-64(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & CH367 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RSVDNCSignal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General.
2WAKE#Digital_IOSignal terminal WAKE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WAKE#. Supported peripheral buses: General.
3PERST#Digital_IOSignal terminal PERST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERST#. Supported peripheral buses: General.
4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6PECKP/PECKNDigital_IOSignal terminal PECKP/PECKN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PECKP/PECKN. Supported peripheral buses: General.
7PECKP/PECKNDigital_IOSignal terminal PECKP/PECKN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PECKP/PECKN. Supported peripheral buses: General.
8VCC18APower_InPrimary positive power supply input (VCC18A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
10GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
11RREFDigital_IOSignal terminal RREF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RREF. Supported peripheral buses: General.
12PERP/PERNDigital_IOSignal terminal PERP/PERN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERP/PERN. Supported peripheral buses: General.
13PERP/PERNDigital_IOSignal terminal PERP/PERN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERP/PERN. Supported peripheral buses: General.
14VCC18APower_InPrimary positive power supply input (VCC18A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
15PETP/PETNDigital_IOSignal terminal PETP/PETN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PETP/PETN. Supported peripheral buses: General.
16PETP/PETNDigital_IOSignal terminal PETP/PETN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PETP/PETN. Supported peripheral buses: General.
17GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
18VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
19GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
20SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: SPI, I2C.
21SDADigital_IOSignal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
22SDXDigital_IOSignal terminal SDX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDX. Supported peripheral buses: SPI.
23SCSDigital_IOSignal terminal SCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS. Supported peripheral buses: SPI.
24INT#Digital_IOSignal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General.
25NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
26NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
27NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
28NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
29VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
30GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
31VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
32GPI2Digital_IOSignal terminal GPI2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPI2. Supported peripheral buses: General.
33GPI1Digital_IOSignal terminal GPI1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPI1. Supported peripheral buses: General.
34D7Digital_IOSignal terminal D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D7. Supported peripheral buses: General.
35D6Digital_IOSignal terminal D6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D6. Supported peripheral buses: General.
36D5Digital_IOSignal terminal D5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5. Supported peripheral buses: General.
37D4Digital_IOSignal terminal D4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D4. Supported peripheral buses: General.
38D3Digital_IOSignal terminal D3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D3. Supported peripheral buses: General.
39D2Digital_IOSignal terminal D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D2. Supported peripheral buses: General.
40D1Digital_IOSignal terminal D1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D1. Supported peripheral buses: General.
41D0Digital_IOSignal terminal D0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D0. Supported peripheral buses: General.
42VCC18Power_InPrimary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
43GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
44IOWRDigital_IOSignal terminal IOWR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IOWR. Supported peripheral buses: General.
45IORDDigital_IOSignal terminal IORD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IORD. Supported peripheral buses: General.
46GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
47VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
48A0Digital_IOSignal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
49A1Digital_IOSignal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
50A2Digital_IOSignal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
51A3Digital_IOSignal terminal A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
52A4Digital_IOSignal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
53A5Digital_IOSignal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
54A6Digital_IOSignal terminal A6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6. Supported peripheral buses: General.
55A7Digital_IOSignal terminal A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7. Supported peripheral buses: General.
56GPO0Digital_IOSignal terminal GPO0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPO0. Supported peripheral buses: General.
57GPO1Digital_IOSignal terminal GPO1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPO1. Supported peripheral buses: General.
58GPODigital_IOSignal terminal GPO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPO. Supported peripheral buses: General.
59VCC33Power_InPrimary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
60GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
61SDIDigital_IOSignal terminal SDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDI. Supported peripheral buses: SPI.
62WAKIN#Digital_IOSignal terminal WAKIN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WAKIN#. Supported peripheral buses: General.
63FIXID#Digital_IOSignal terminal FIXID# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FIXID#. Supported peripheral buses: General.
64RSTODigital_IOSignal terminal RSTO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSTO. Supported peripheral buses: General.
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