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ATMEGA8535L-8PU (PDIP-40) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATMEGA8535L-8PU

MICROCHIPID: C185629PDIP-40 · 40 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATMEGA8535L-8PU (PDIP-40)1(XCK/T0)PB02(T1)PB13(INT2/AIN0)P4(OC0/AIN1)PB5(#SS)PB46(MOSI)PB57(MISO)PB68(SCK)PB79#RESET10VCC11GND12XTAL213XTAL114(RXD)PD015(TXD)PD116(INT0)PD217(INT1)PD318(OC1B)PD419(OC1A)PD520(ICP1)PD640PA0(ADC0)39PA1(ADC1)38PA2(ADC2)37PA3(ADC3)36PA4(ADC4)35PA5(ADC5)34PA6(ADC6)33PA7(ADC7)32AREF31GND30AVCC29PC7(TOSC2)28PC6(TOSC1)27PC526PC425PC324PC223PC1(SDA)22PC0(SCL)21PD7(OC2)Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.830.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940E=10.00mm · Pitch e=2.54mmD=10.00mm-22-20-18-16-14-12-10-8-6-4-2024681012141618202238363432302826242220181614121086420-2-4-6-8-10-12-14-16-18-20-22-24-26-28-30-32-34-36-38mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (40/40)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1(XCK/T0)PB0I/OMultiplexed I/O & Peripheral Pin (XCK/T0)PB0 (General)
2(T1)PB1I/OMultiplexed I/O & Peripheral Pin (T1)PB1 (General)
3(INT2/AIN0)PB2I/OMultiplexed I/O & Peripheral Pin (INT2/AIN0)PB2 (ADC)
4(OC0/AIN1)PB3I/OMultiplexed I/O & Peripheral Pin (OC0/AIN1)PB3 (ADC)
5(#SS)PB4I/OMultiplexed I/O & Peripheral Pin (#SS)PB4 (General)
6(MOSI)PB5I/OMultiplexed I/O & Peripheral Pin (MOSI)PB5 (SPI)
7(MISO)PB6I/OMultiplexed I/O & Peripheral Pin (MISO)PB6 (SPI)
8(SCK)PB7I/OMultiplexed I/O & Peripheral Pin (SCK)PB7 (SPI)
9#RESETISystem Enable & Hardware Reset (#RESET)
10VCCPowerPower Supply Input (VCC — 1.8V ~ 5.5V VCC)
11GNDGNDGround Reference Pin (GND)
12XTAL2I/OMultiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)
13XTAL1I/OMultiplexed I/O & Peripheral Pin XTAL1 (RTC/CLK)
14(RXD)PD0I/OMultiplexed I/O & Peripheral Pin (RXD)PD0 (UART)
15(TXD)PD1I/OMultiplexed I/O & Peripheral Pin (TXD)PD1 (UART)
16(INT0)PD2I/OMultiplexed I/O & Peripheral Pin (INT0)PD2 (General)
17(INT1)PD3I/OMultiplexed I/O & Peripheral Pin (INT1)PD3 (General)
18(OC1B)PD4I/OMultiplexed I/O & Peripheral Pin (OC1B)PD4 (PWM)
19(OC1A)PD5I/OMultiplexed I/O & Peripheral Pin (OC1A)PD5 (PWM)
20(ICP1)PD6I/OMultiplexed I/O & Peripheral Pin (ICP1)PD6 (General)
21PD7(OC2)I/OMultiplexed I/O & Peripheral Pin PD7(OC2) (General)
22PC0(SCL)I/OMultiplexed I/O & Peripheral Pin PC0(SCL) (I2C)
23PC1(SDA)I/OMultiplexed I/O & Peripheral Pin PC1(SDA) (I2C)
24PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
25PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
26PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
27PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
28PC6(TOSC1)I/OMultiplexed I/O & Peripheral Pin PC6(TOSC1) (General)
29PC7(TOSC2)I/OMultiplexed I/O & Peripheral Pin PC7(TOSC2) (General)
30AVCCPowerPower Supply Input (AVCC — 1.8V ~ 5.5V VCC)
31GNDGNDGround Reference Pin (GND)
32AREFI/OMultiplexed I/O & Peripheral Pin AREF (ADC)
33PA7(ADC7)I/OMultiplexed I/O & Peripheral Pin PA7(ADC7) (ADC)
34PA6(ADC6)I/OMultiplexed I/O & Peripheral Pin PA6(ADC6) (ADC)
35PA5(ADC5)I/OMultiplexed I/O & Peripheral Pin PA5(ADC5) (ADC)
36PA4(ADC4)I/OMultiplexed I/O & Peripheral Pin PA4(ADC4) (ADC)
37PA3(ADC3)I/OMultiplexed I/O & Peripheral Pin PA3(ADC3) (ADC)
38PA2(ADC2)I/OMultiplexed I/O & Peripheral Pin PA2(ADC2) (ADC)
39PA1(ADC1)I/OMultiplexed I/O & Peripheral Pin PA1(ADC1) (ADC)
40PA0(ADC0)I/OMultiplexed I/O & Peripheral Pin PA0(ADC0) (ADC)
PIN 1 (XCK/T0)PB0
I/O
Multiplexed I/O & Peripheral Pin (XCK/T0)PB0 (General)
Design note: Signal terminal (XCK/T0)PB0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (XCK/T0)PB0. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATMEGA8535L-8PU (MICROCHIP · PDIP-40)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATMEGA8535L-8PU (PDIP-40) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATMEGA8535L-8PU (PDIP-40) - 2. Standard Pinout (Top View)
True package pinout (40 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATMEGA8535L-8PU (PDIP-40) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATMEGA8535L-8PU (PDIP-40) - 4. Package Dimensions (D×E×A)
PDIP-40 · 10.00×10.00mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATMEGA8535L-8PU (PDIP-40) - 5. Recommended Land Pattern
IPC-7351B Footprint (40 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATMEGA8535L-8PU (PDIP-40) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for ATMEGA8535L
P1 · p01_fig01652×576px
ATMEGA8535L-8PU (PDIP-40) — 8-bit Microcontroller with 8K Bytes In-System Programmable Flash
8-bit Microcontroller with 8K Bytes In-System Programmable Flash
P2 · p02_fig011440×1492px
ATMEGA8535L-8PU (PDIP-40) — Pin Configurations Figure 1. Pinout ATmega8535 | (XCK/T0) PB0 | (T1) PB1 (INT2/AIN0) PB2 | (OC0/AIN1) PB3 | (SS) PB4 (MOSI) PB5 (MISO) PB6 | (SCK) PB7 | RESET | VCC GND XTAL2 XTAL1 (RXD) PD0 | (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1
Pin Configurations Figure 1. Pinout ATmega8535 | (XCK/T0) PB0 | (T1) PB1 (INT2/AIN0) PB2 | (OC0/AIN1) PB3 | (SS) PB4 (MOSI) PB5 (MISO) PB6 | (SCK) PB7 | RESET | VCC GND XTAL2 XTAL1 (RXD) PD0 | (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1
P2 · p02_fig01P2
ATMEGA8535L-8PU (PDIP-40) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P15 · p15_fig012123×2388px
ATMEGA8535L-8PU (PDIP-40) — 15
15
P15 · p15_fig01P15
ATMEGA8535L-8PU (PDIP-40) — Datasheet Page 15 (p15_fig01)
Datasheet Page 15 (p15_fig01)
P16 · p16_fig011979×2182px
ATMEGA8535L-8PU (PDIP-40) — 16 ATmega8535(L)
16 ATmega8535(L)

Technical Specifications & Part Details (ATMEGA8535L-8PU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:ATMEGA8535L-8PU (PDIP-40) is a 40-pin embedded microcontroller unit (mcu) featuring a 10.00 × 10.00 × 3.85 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
16 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
40 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 3.85 mm (A1=0.51 mm)
Package family: DIP (PDIP-40)
Pin Count & Lead PitchN / e
40 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol40 auto-grouped pins
OK
IPC-7351B Land Pattern40 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-40)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=3.85mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
40P / 40Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PDIP-40
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATMEGA8535L-8PU (PDIP-40)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATMEGA8535L-8PU (PDIP-40)?

Manufactured by MICROCHIP, the ATMEGA8535L-8PU is housed in a PDIP-40 package with 40 pins and a 2.54 mm lead pitch. Key pins include: 1 ((XCK/T0)PB0: Multiplexed I/O & Peripheral Pin (XCK/T0)PB0 (General)), 2 ((T1)PB1: Multiplexed I/O & Peripheral Pin (T1)PB1 (General)), 3 ((INT2/AIN0)PB2: Multiplexed I/O & Peripheral Pin (INT2/AIN0)PB2 (ADC)), 4 ((OC0/AIN1)PB3: Multiplexed I/O & Peripheral Pin (OC0/AIN1)PB3 (ADC)), 5 ((#SS)PB4: Multiplexed I/O & Peripheral Pin (#SS)PB4 (General)), 6 ((MOSI)PB5: Multiplexed I/O & Peripheral Pin (MOSI)PB5 (SPI)).

What are the IPC-7351B PCB Footprint dimensions for ATMEGA8535L-8PU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATMEGA8535L-8PU (PDIP-40) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 2.54 mm, and 40 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATMEGA8535L-8PU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATMEGA8535L-8PU (MICROCHIP, PDIP-40) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (40 pins) & ATMEGA8535L Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1(XCK/T0)PB0Digital_IOSignal terminal (XCK/T0)PB0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (XCK/T0)PB0. Supported peripheral buses: General.
2(T1)PB1Digital_IOSignal terminal (T1)PB1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (T1)PB1. Supported peripheral buses: General.
3(INT2/AIN0)PB2AnalogSignal terminal (INT2/AIN0)PB2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (INT2/AIN0)PB2. Supported peripheral buses: ADC.
4(OC0/AIN1)PB3AnalogSignal terminal (OC0/AIN1)PB3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (OC0/AIN1)PB3. Supported peripheral buses: ADC.
5(#SS)PB4Digital_IOSignal terminal (#SS)PB4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (#SS)PB4. Supported peripheral buses: General.
6(MOSI)PB5Digital_IOSignal terminal (MOSI)PB5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (MOSI)PB5. Supported peripheral buses: SPI.
7(MISO)PB6Digital_IOSignal terminal (MISO)PB6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (MISO)PB6. Supported peripheral buses: SPI.
8(SCK)PB7Digital_IOSignal terminal (SCK)PB7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (SCK)PB7. Supported peripheral buses: SPI.
9#RESETDigital_IOActive-low hardware reset terminal (#RESET): pulling this pin Low resets the processor core and peripherals.
10VCCPower_InPrimary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
11GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
12XTAL2Digital_IOSignal terminal XTAL2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: XTAL2. Supported peripheral buses: RTC/CLK.
13XTAL1Digital_IOSignal terminal XTAL1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: XTAL1. Supported peripheral buses: RTC/CLK.
14(RXD)PD0Digital_IOSignal terminal (RXD)PD0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (RXD)PD0. Supported peripheral buses: UART.
15(TXD)PD1Digital_IOSignal terminal (TXD)PD1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (TXD)PD1. Supported peripheral buses: UART.
16(INT0)PD2Digital_IOSignal terminal (INT0)PD2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (INT0)PD2. Supported peripheral buses: General.
17(INT1)PD3Digital_IOSignal terminal (INT1)PD3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (INT1)PD3. Supported peripheral buses: General.
18(OC1B)PD4Digital_IOSignal terminal (OC1B)PD4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (OC1B)PD4. Supported peripheral buses: PWM.
19(OC1A)PD5Digital_IOSignal terminal (OC1A)PD5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (OC1A)PD5. Supported peripheral buses: PWM.
20(ICP1)PD6Digital_IOSignal terminal (ICP1)PD6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: (ICP1)PD6. Supported peripheral buses: General.
21PD7(OC2)Digital_IOSignal terminal PD7(OC2) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD7(OC2). Supported peripheral buses: General.
22PC0(SCL)Digital_IOSignal terminal PC0(SCL) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC0(SCL). Supported peripheral buses: I2C.
23PC1(SDA)Digital_IOSignal terminal PC1(SDA) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC1(SDA). Supported peripheral buses: I2C.
24PC2Digital_IOSignal terminal PC2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
25PC3Digital_IOSignal terminal PC3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
26PC4Digital_IOSignal terminal PC4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
27PC5Digital_IOSignal terminal PC5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
28PC6(TOSC1)Digital_IOSignal terminal PC6(TOSC1) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC6(TOSC1). Supported peripheral buses: General.
29PC7(TOSC2)Digital_IOSignal terminal PC7(TOSC2) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC7(TOSC2). Supported peripheral buses: General.
30AVCCPower_InPrimary positive power supply input (AVCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
31GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
32AREFDigital_IOSignal terminal AREF (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: AREF. Supported peripheral buses: ADC.
33PA7(ADC7)AnalogSignal terminal PA7(ADC7) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA7(ADC7). Supported peripheral buses: ADC.
34PA6(ADC6)AnalogSignal terminal PA6(ADC6) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA6(ADC6). Supported peripheral buses: ADC.
35PA5(ADC5)AnalogSignal terminal PA5(ADC5) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA5(ADC5). Supported peripheral buses: ADC.
36PA4(ADC4)AnalogSignal terminal PA4(ADC4) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA4(ADC4). Supported peripheral buses: ADC.
37PA3(ADC3)AnalogSignal terminal PA3(ADC3) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA3(ADC3). Supported peripheral buses: ADC.
38PA2(ADC2)AnalogSignal terminal PA2(ADC2) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA2(ADC2). Supported peripheral buses: ADC.
39PA1(ADC1)AnalogSignal terminal PA1(ADC1) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA1(ADC1). Supported peripheral buses: ADC.
40PA0(ADC0)AnalogSignal terminal PA0(ADC0) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA0(ADC0). Supported peripheral buses: ADC.
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