STM32L083RZT6TR (LQFP-64(10x10)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of STM32L083RZT6TR (LQFP-64(10x10))?

Manufactured by ST, the STM32L083RZT6TR is housed in a LQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: 1 (VLCD: Multiplexed I/O & Peripheral Pin VLCD (General)), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14 - OSC32_IN (PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)), 4 (NC: No Connect (Leave Floating)), 5 (PH0OSC IN -_ (PH0): Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (USB, RTC/CLK)), 6 (PH1 - OSC_OUT (PH1): Multiplexed I/O & Peripheral Pin PH1 - OSC_OUT (PH1) (RTC/CLK)).

Q: What are the IPC-7351B PCB Footprint dimensions for STM32L083RZT6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L083RZT6TR (LQFP-64(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L083RZT6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L083RZT6TR (ST, LQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	VLCD	I/O	Multiplexed I/O & Peripheral Pin VLCD (General)
2	PC13	I/O	Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
3	PC14 - OSC32_IN (PC14)	I/O	Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
4	NC	NC	No Connect (Leave Floating)
5	PH0OSC IN -_ (PH0)	I/O	Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (USB, RTC/CLK)
6	PH1 - OSC_OUT (PH1)	I/O	Multiplexed I/O & Peripheral Pin PH1 - OSC_OUT (PH1) (RTC/CLK)
7	NRST	I	System Enable & Hardware Reset (NRST)
8	PC0	I/O	Multiplexed I/O & Peripheral Pin PC0 (I2C, ADC)
9	PC1	I/O	Multiplexed I/O & Peripheral Pin PC1 (I2C, ADC)
10	PC2	I/O	Multiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
11	PC3	I/O	Multiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
12	VSSA	GND	Ground Reference Pin (VSSA)
13	VDDA	Power	Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))
14	PA0	I/O	Multiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
15	PA1	I/O	Multiplexed I/O & Peripheral Pin PA1 (UART)
16	PA2	I/O	Multiplexed I/O & Peripheral Pin PA2 (UART, ADC)
17	PA3	I/O	Multiplexed I/O & Peripheral Pin PA3 (UART)
18	VSS	GND	Ground Reference Pin (VSS)
19	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
20	PA4	I/O	Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
21	PA5	I/O	Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
22	PA6	I/O	Multiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
23	PA7	I/O	Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
24	PC4	I/O	Multiplexed I/O & Peripheral Pin PC4 (ADC)
25	PC5	I/O	Multiplexed I/O & Peripheral Pin PC5 (ADC)
26	PB0	I/O	Multiplexed I/O & Peripheral Pin PB0 (ADC)
27	PB1	I/O	Multiplexed I/O & Peripheral Pin PB1 (UART, ADC)
28	PB2	I/O	Multiplexed I/O & Peripheral Pin PB2 (I2C)
29	PB10	I/O	Multiplexed I/O & Peripheral Pin PB10 (SPI, PWM)
30	PB11	I/O	Multiplexed I/O & Peripheral Pin PB11 (I2C, PWM)
31	VSS	GND	Ground Reference Pin (VSS)
32	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
33	PB12	I/O	Multiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
34	PB13	I/O	Multiplexed I/O & Peripheral Pin PB13 (UART, SPI, I2C)
35	PB14	I/O	Multiplexed I/O & Peripheral Pin PB14 (UART, SPI, I2C)
36	PB15	I/O	Multiplexed I/O & Peripheral Pin PB15 (SPI, RTC/CLK)
37	PC6	I/O	Multiplexed I/O & Peripheral Pin PC6 (PWM)
38	PC7	I/O	Multiplexed I/O & Peripheral Pin PC7 (PWM)
39	PC8	I/O	Multiplexed I/O & Peripheral Pin PC8 (PWM)
40	PC9	I/O	Multiplexed I/O & Peripheral Pin PC9 (USB, I2C, PWM)
41	PA8	I/O	Multiplexed I/O & Peripheral Pin PA8 (USB, UART, RTC/CLK)
42	PA9	I/O	Multiplexed I/O & Peripheral Pin PA9 (UART, I2C, RTC/CLK)
43	PA10	I/O	Multiplexed I/O & Peripheral Pin PA10 (UART)
44	PA11	I/O	Multiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI)
45	PA12	I/O	Multiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI)
46	PA13	I/O	Multiplexed I/O & Peripheral Pin PA13 (USB, SWD/JTAG)
47	VSS	GND	Ground Reference Pin (VSS)
48	VDD_USB	Power	Power Supply Input (VDD_USB — 3.3V VDD (Max 4.0V))
49	PA14	I/O	Multiplexed I/O & Peripheral Pin PA14 (UART, SWD/JTAG)
50	PA15	I/O	Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM)
51	PC10	I/O	Multiplexed I/O & Peripheral Pin PC10 (UART)
52	PC11	I/O	Multiplexed I/O & Peripheral Pin PC11 (UART)
53	PC12	I/O	Multiplexed I/O & Peripheral Pin PC12 (UART)
54	PD2	I/O	Multiplexed I/O & Peripheral Pin PD2 (UART)
55	PB3	I/O	Multiplexed I/O & Peripheral Pin PB3 (UART, SPI, PWM)
56	PB4	I/O	Multiplexed I/O & Peripheral Pin PB4 (UART, SPI)
57	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C)
58	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (UART)
59	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (UART, I2C)
60	BOOT0	I	Input-Only Pin BOOT0 (General)
61	PB8	I/O	Multiplexed I/O & Peripheral Pin PB8 (General)
62	PB9	I/O	Multiplexed I/O & Peripheral Pin PB9 (SPI, I2C)
63	VSS	GND	Ground Reference Pin (VSS)
64	VDD	Power	Power Supply Input (VDD — 3.3V VDD (Max 4.0V))

PIN 1 VLCD

I/O

Multiplexed I/O & Peripheral Pin VLCD (General)

Design note: Signal terminal VLCD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLCD. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

STM32L083RZT6TR (LQFP-64(10x10)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

STM32L083RZT6TR (LQFP-64(10x10)) - 2. Standard Pinout (Top View)

True package pinout (64 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

STM32L083RZT6TR (LQFP-64(10x10)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

STM32L083RZT6TR (LQFP-64(10x10)) - 4. Package Dimensions (D×E×A)

LQFP-64(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

STM32L083RZT6TR (LQFP-64(10x10)) - 5. Recommended Land Pattern

IPC-7351B Footprint (64 Pads)Expand ›

6. Application SchematicSCHEMATIC

STM32L083RZT6TR (LQFP-64(10x10)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)

Showing 1–12 of 16 uncropped original figures for STM32L083

P1 · p01_fig01EXACT PACKAGE

STM32L083xZ Ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+, up to 192KB

P39 · p39_fig01EXACT PACKAGE

STM32L083RZT6TR (LQFP-64(10x10)) — Figure 5. STM32L083xx LQFP64 pinout VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28

Figure 5. STM32L083xx LQFP64 pinout VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28

P130 · p130_fig01EXACT PACKAGE

Figure 45. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline SEATING PLANE C

P131 · p131_fig01EXACT PACKAGE

Figure 46. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint

P1 · p01_fig02890×359px

• Hardware Encryption Engine AES 128-bit

P39 · p39_fig01P39

Datasheet Page 39 (p39_fig01)

P60 · p60_fig011546×1527px

Figure 11. Power supply scheme

P60 · p60_fig01P60

Datasheet Page 60 (p60_fig01)

P61 · p61_fig011546×975px

Figure 12. Optional LCD power supply scheme

P61 · p61_fig021546×555px

Figure 13. Current consumption measurement scheme

P105 · p105_fig011546×705px

Figure 29. Typical connection diagram using the ADC

P105 · p105_fig021546×975px

Figure 30. Power supply and reference decoupling (VREF+ not connected to VDDA)

Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (STM32L083RZT6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Embedded Microcontroller Unit (MCU)

Detailed Overview:STM32L083RZT6TR (LQFP-64(10x10)) is a 64-pin embedded microcontroller unit (mcu) featuring a 10.00 × 10.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.65 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.

Operating Supply VoltageV_CC / V_DD

1.65 V to 3.6 V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

32 kHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

45 5V-tolerant (FT) pins detected

Package Envelope (D × E × A)D × E × A

10.00 × 10.00 × 1.60 mm (A1=0.10 mm)

Package family: LQFP (LQFP-64(10x10))

Pin Count & Lead PitchN / e

64 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, UART, SPI, I2C, I2S, ADC, DAC, IrDA, PWM, RTC/CLK, SWD/JTAG

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol64 auto-grouped pins

IPC-7351B Land Pattern64 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-64(10x10))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

10.00 × 10.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.60mm · e=0.50mm

Pad Size (W × L)Level B

0.30 × 1.20 mm

Pins / Total PadsTopology

64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit LQFP-64(10x10)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L083RZT6TR (LQFP-64(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L083RZT6TR (LQFP-64(10x10))?

Manufactured by ST, the STM32L083RZT6TR is housed in a LQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: 1 (VLCD: Multiplexed I/O & Peripheral Pin VLCD (General)), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14 - OSC32_IN (PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)), 4 (NC: No Connect (Leave Floating)), 5 (PH0OSC IN -_ (PH0): Multiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (USB, RTC/CLK)), 6 (PH1 - OSC_OUT (PH1): Multiplexed I/O & Peripheral Pin PH1 - OSC_OUT (PH1) (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32L083RZT6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L083RZT6TR (LQFP-64(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L083RZT6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L083RZT6TR (ST, LQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32L083 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	VLCD	Digital_IO	Signal terminal VLCD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLCD. Supported peripheral buses: General.
2	PC13	Digital_IO	Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
3	PC14 - OSC32_IN (PC14)	Digital_IO	Signal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
4	NC	No_Connect	No Connect (Leave Floating)
5	PH0OSC IN -_ (PH0)	Digital_IO	Signal terminal PH0OSC IN -_ (PH0) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0OSC IN -_ (PH0). Supported peripheral buses: USB, RTC/CLK.
6	PH1 - OSC_OUT (PH1)	Digital_IO	Signal terminal PH1 - OSC_OUT (PH1) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1 - OSC_OUT (PH1). Supported peripheral buses: RTC/CLK.
7	NRST	Digital_IO	Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8	PC0	Digital_IO	Signal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL. Supported peripheral buses: I2C, ADC.
9	PC1	Digital_IO	Signal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA. Supported peripheral buses: I2C, ADC.
10	PC2	Digital_IO	Signal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC.
11	PC3	Digital_IO	Signal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC.
12	VSSA	GND	0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
13	VDDA	Power_In	Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
14	PA0	Digital_IO	Signal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
15	PA1	Digital_IO	Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART.
16	PA2	Digital_IO	Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC.
17	PA3	Digital_IO	Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART.
18	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
19	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
20	PA4	Digital_IO	Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC.
21	PA5	Digital_IO	Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCKTIM2ETR. Supported peripheral buses: SPI, ADC, PWM.
22	PA6	Digital_IO	Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC.
23	PA7	Digital_IO	Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC.
24	PC4	Digital_IO	Signal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
25	PC5	Digital_IO	Signal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
26	PB0	Digital_IO	Signal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC.
27	PB1	Digital_IO	Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC.
28	PB2	Digital_IO	Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: I2C.
29	PB10	Digital_IO	Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKI2C2SCL. Supported peripheral buses: SPI, PWM.
30	PB11	Digital_IO	Signal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: I2C, PWM.
31	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
33	PB12	Digital_IO	Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA. Supported peripheral buses: UART, SPI, I2C.
34	PB13	Digital_IO	Signal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, I2C.
35	PB14	Digital_IO	Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, I2C.
36	PB15	Digital_IO	Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, RTC/CLK.
37	PC6	Digital_IO	Signal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
38	PC7	Digital_IO	Signal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
39	PC8	Digital_IO	Signal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM.
40	PC9	Digital_IO	Signal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA. Supported peripheral buses: USB, I2C, PWM.
41	PA8	Digital_IO	Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: USB, UART, RTC/CLK.
42	PA9	Digital_IO	Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: UART, I2C, RTC/CLK.
43	PA10	Digital_IO	Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
44	PA11	Digital_IO	Signal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, USB_DM. Supported peripheral buses: USB, UART, SPI.
45	PA12	Digital_IO	Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, USB_DP. Supported peripheral buses: USB, UART, SPI.
46	PA13	Digital_IO	Signal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: USB, SWD/JTAG.
47	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
48	VDD_USB	Power_In	Primary positive power supply input (VDD_USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
49	PA14	Digital_IO	Signal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: UART, SWD/JTAG.
50	PA15	Digital_IO	Signal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, PWM.
51	PC10	Digital_IO	Signal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: UART.
52	PC11	Digital_IO	Signal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART.
53	PC12	Digital_IO	Signal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: UART.
54	PD2	Digital_IO	Signal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
55	PB3	Digital_IO	Signal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCKLCDSEG7. Supported peripheral buses: UART, SPI, PWM.
56	PB4	Digital_IO	Signal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI.
57	PB5	Digital_IO	Signal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C1_SMBA. Supported peripheral buses: UART, SPI, I2C.
58	PB6	Digital_IO	Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART.
59	PB7	Digital_IO	Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART, I2C.
60	BOOT0	Digital_IO	Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
61	PB8	Digital_IO	Signal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
62	PB9	Digital_IO	Signal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, SPI2_NSS. Supported peripheral buses: SPI, I2C.
63	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
64	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).

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