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STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L151UCY6TR

STID: C1852729WLCSP-63(3.2x4.2) · 63 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L151UCY6TR (WLCSP-63(3.2x4.2))A1VSS_2A2PA15A3PC11A4PD2A5PB5A6BOOT0A7VSS_3B1PA11B2VDD_2B3PC10B4PC12B5PB6B6PB8B7VDD_3C1PA9C2PA13C3PA14C4PB3C5PB7C6PB9C7V (3) LCDD1PC8D2PA10D3PA12D4PB4D5PC13 - WKUP2D6PC15 - OSC32D7PC14 - OSC32E1PC7E2PC9E3PA8E4PA0WKUP1 -J7PA3J6PA4J5PA7J4PC5J3PB0J2PB10J1VSS_1H7VDDAH6PA2H5VSSH4PA5H3PB1H2PB11H1VDD_1G7PC2G6PC3G5PA1G4PA6G3PB2G2PB12G1PB13F7PH1 - OSC OUF6PH0 - OSC INF5VSSAF4PC4F3PB14F2PB15F1PC6E7NRSTE6PC0E5PC1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1A2B2C2D2E2F2G2H2J2A3B3C3D3E3F3G3H3J3A4B4C4D4E4F4G4H4J4A5B5C5D5E5F5G5H5J5A6B6C6D6E6F6G6H6J6A7B7C7D7E7F7G7H7J7E=3.20mm · Pitch e=0.40mmD=4.20mm-3-2-1012343210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.20mm × 4.20mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (63/63)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VSS_2GNDGround Reference Pin (VSS_2)
A2PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SPI, SWD/JTAG)
A3PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
A4PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
A5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
A6BOOT0IInput-Only Pin BOOT0 (General)
A7VSS_3GNDGround Reference Pin (VSS_3)
B1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI)
B2VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
B3PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
B4PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
B6PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
B7VDD_3PowerPower Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
C1PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART)
C2PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
C3PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
C4PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, SWD/JTAG)
C5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
C6PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C)
C7V (3) LCDI/OMultiplexed I/O & Peripheral Pin V (3) LCD (General)
D1PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
D2PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
D3PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI)
D4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)
D5PC13 - WKUP2I/OMultiplexed I/O & Peripheral Pin PC13 - WKUP2 (RTC/CLK)
D6PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
D7PC14 - OSC32 IN(4)_I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32 IN(4)_ (RTC/CLK)
E1PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E2PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E3PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
E4PA0WKUP1 -I/OMultiplexed I/O & Peripheral Pin PA0WKUP1 - (UART, ADC, RTC/CLK)
E5PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
E6PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
E7NRSTISystem Enable & Hardware Reset (NRST)
F1PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
F2PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, ADC, RTC/CLK)
F3PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, ADC)
F4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
F5VSSAGNDGround Reference Pin (VSSA)
F6PH0 - OSC IN(5)_I/OMultiplexed I/O & Peripheral Pin PH0 - OSC IN(5)_ (RTC/CLK)
F7PH1 - OSC OUT(5)_I/OMultiplexed I/O & Peripheral Pin PH1 - OSC OUT(5)_ (RTC/CLK)
G1PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, ADC)
G2PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C, ADC)
G3PB2I/OMultiplexed I/O & Peripheral Pin PB2 (ADC)
G4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
G5PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
G6PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
G7PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
H1VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
H2PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
H3PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC)
H4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC)
H5VSSGNDGround Reference Pin (VSS)
H6PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
H7VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
J1VSS_1GNDGround Reference Pin (VSS_1)
J2PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
J3PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC)
J4PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
J5PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
J6PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
J7PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC)
PIN A1 VSS_2
GND
Ground Reference Pin (VSS_2)
Design note: VSS_2
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L151UCY6TR (ST · WLCSP-63(3.2x4.2))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) - 2. Standard Pinout (Top View)
True package pinout (63 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) - 4. Package Dimensions (D×E×A)
WLCSP-63(3.2x4.2) · 3.20×4.20mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) - 5. Recommended Land Pattern
IPC-7351B Footprint (63 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for STM32L151 / STM32L152
P1 · p01_fig01EXACT PACKAGE
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3, 256KB Flash, 32KB SRAM, 8KB EEPROM, LCD, USB, ADC, DAC | Datasheet - production data | LQFP100 (14 × 14 mm) LQFP64 (10 × 10 mm) LQFP48 (7 x 7 mm) | UFBGA100 | (7 x 7 mm) | WLCSP63 (0.4 mm pi
Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3, 256KB Flash, 32KB SRAM, 8KB EEPROM, LCD, USB, ADC, DAC | Datasheet - production data | LQFP100 (14 × 14 mm) LQFP64 (10 × 10 mm) LQFP48 (7 x 7 mm) | UFBGA100 | (7 x 7 mm) | WLCSP63 (0.4 mm pi
P1 · p01_fig02EXACT PACKAGE
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — August 2017 DocID022799 Rev 13 1/136
August 2017 DocID022799 Rev 13 1/136
P35 · p35_fig01EXACT PACKAGE
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Figure 6. STM32L15xUC WLCSP63 ballout       
Figure 6. STM32L15xUC WLCSP63 ballout       
P32 · p32_fig011649×1655px
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Figure 3. STM32L15xVC UFBGA100 ballout
Figure 3. STM32L15xVC UFBGA100 ballout
P35 · p35_fig01P35
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Datasheet Page 35 (p35_fig01)
Datasheet Page 35 (p35_fig01)
P53 · p53_fig011546×1260px
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Figure 12. Power supply scheme
Figure 12. Power supply scheme
P53 · p53_fig01P53
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Datasheet Page 53 (p53_fig01)
Datasheet Page 53 (p53_fig01)
P54 · p54_fig011546×1124px
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Figure 13. Optional LCD power supply scheme
Figure 13. Optional LCD power supply scheme
P54 · p54_fig021546×814px
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Figure 14. Current consumption measurement scheme
Figure 14. Current consumption measurement scheme
P76 · p76_fig011546×548px
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Figure 18. Typical application with a 32.768 kHz crystal
Figure 18. Typical application with a 32.768 kHz crystal
P101 · p101_fig011543×856px
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Figure 28. ADC accuracy characteristics
Figure 28. ADC accuracy characteristics
P101 · p101_fig021546×557px
STM32L151UCY6TR (WLCSP-63(3.2x4.2)) — Figure 29. Typical connection diagram using the ADC
Figure 29. Typical connection diagram using the ADC
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (STM32L151UCY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L151UCY6TR (WLCSP-63(3.2x4.2)) is a 63-pin embedded microcontroller unit (mcu) featuring a 4.20 × 3.20 × 0.57 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.65 V to 3.6 V supply operation across -40 °C to 105 °C with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.65 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40 °C to 105 °C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
42 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
4.20 × 3.20 × 0.57 mm (A1=0.19 mm)
Package family: WLCSP (WLCSP-63(3.2x4.2))
Pin Count & Lead PitchN / e
63 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol63 auto-grouped pins
OK
IPC-7351B Land Pattern63 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-63(3.2x4.2))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.20 × 3.20 mm
Height (A) & Pitch (e)IPC-7351B
A=0.57mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.22 mm
Pins / Total PadsTopology
63P / 63Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-63(3.2x4.2)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L151UCY6TR (WLCSP-63(3.2x4.2))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L151UCY6TR (WLCSP-63(3.2x4.2))?

Manufactured by ST, the STM32L151UCY6TR is housed in a WLCSP-63(3.2x4.2) package with 63 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: A1 (VSS_2: Ground Reference Pin (VSS_2)), A2 (PA15: Multiplexed I/O & Peripheral Pin PA15 (SPI, SWD/JTAG)), A3 (PC11: Multiplexed I/O & Peripheral Pin PC11 (UART, SPI)), A4 (PD2: Multiplexed I/O & Peripheral Pin PD2 (General)), A5 (PB5: Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C)), A6 (BOOT0: Input-Only Pin BOOT0 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32L151UCY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L151UCY6TR (WLCSP-63(3.2x4.2)) has a nominal body envelope of 3.20 × 4.20 mm, pitch e = 0.40 mm, and 63 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L151UCY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L151UCY6TR (ST, WLCSP-63(3.2x4.2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (63 pins) & STM32L151 / STM32L152 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
A2PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: SPI, SWD/JTAG.
A3PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI.
A4PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
A5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, SPI3_MOSI_. Supported peripheral buses: SPI, I2C.
A6BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A7VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
B1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, USB_DM. Supported peripheral buses: USB, UART, SPI.
B2VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B3PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
B4PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
B6PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
B7VDD_3Power_InPrimary positive power supply input (VDD_3) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C1PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART.
C2PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
C3PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
C4PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, SPI3_SCK. Supported peripheral buses: SPI, SWD/JTAG.
C5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
C6PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
C7V (3) LCDDigital_IOSignal terminal V (3) LCD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: V (3) LCD. Supported peripheral buses: General.
D1PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
D2PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
D3PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, USB_DP. Supported peripheral buses: USB, UART, SPI.
D4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, SPI3_MISO. Supported peripheral buses: SPI, SWD/JTAG.
D5PC13 - WKUP2Digital_IOSignal terminal PC13 - WKUP2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13 - WKUP2. Supported peripheral buses: RTC/CLK.
D6PC15 - OSC32_OUTDigital_IOSignal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK.
D7PC14 - OSC32 IN(4)_Digital_IOSignal terminal PC14 - OSC32 IN(4)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14 - OSC32 IN(4)_. Supported peripheral buses: RTC/CLK.
E1PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E2PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E3PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
E4PA0WKUP1 -Digital_IOSignal terminal PA0WKUP1 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0WKUP1 -. Supported peripheral buses: UART, ADC, RTC/CLK.
E5PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
E6PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
E7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F1PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
F2PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI_. Supported peripheral buses: SPI, ADC, RTC/CLK.
F3PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, ADC.
F4PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
F5VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
F6PH0 - OSC IN(5)_Digital_IOSignal terminal PH0 - OSC IN(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0 - OSC IN(5)_. Supported peripheral buses: RTC/CLK.
F7PH1 - OSC OUT(5)_Digital_IOSignal terminal PH1 - OSC OUT(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1 - OSC OUT(5)_. Supported peripheral buses: RTC/CLK.
G1PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, ADC.
G2PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SMBA, SPI2_NSS. Supported peripheral buses: UART, SPI, I2C, ADC.
G3PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: ADC.
G4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC.
G5PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC.
G6PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
G7PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
H1VDD_1Power_InPrimary positive power supply input (VDD_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H2PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, I2C.
H3PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC.
H4PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC.
H5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
H6PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC.
H7VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
J1VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
J2PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C.
J3PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC.
J4PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
J5PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC.
J6PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
J7PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC.
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