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LX7220-03ILQ-TR (VQFN-14(2x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

LX7220-03ILQ-TR

MICROCHIPID: C1849551VQFN-14(2x3) · 15 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · LX7220-03ILQ-TR (VQFN-14(2x3))1PGOOD2SDA3GND4SW5VIN6VIN7VIN8VIN15GND14AVIN13SCL12VOUT11AGND10EN9SWGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.815.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
157613141211109854321E=2.00mm · Pitch e=0.50mmD=3.00mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.00mm × 3.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (15/15)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PGOODI/OMultiplexed I/O & Peripheral Pin PGOOD (General)
2SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
3GNDGNDGround Reference Pin (GND)
4SWI/OMultiplexed I/O & Peripheral Pin SW (General)
5VINPowerPower Supply Input (VIN — 2.7V to 5.5V)
6VINPowerPower Supply Input (VIN — 2.7V to 5.5V)
7VINPowerPower Supply Input (VIN — 2.7V to 5.5V)
8VINPowerPower Supply Input (VIN — 2.7V to 5.5V)
9SWI/OMultiplexed I/O & Peripheral Pin SW (General)
10ENISystem Enable & Hardware Reset (EN)
11AGNDGNDGround Reference Pin (AGND)
12VOUTPowerRegulated Power Output (VOUT — 2.7V to 5.5V)
13SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
14AVINPowerPower Supply Input (AVIN — 2.7V to 5.5V)
15GNDGNDGround Reference Pin (GND)
PIN 1 PGOOD
I/O
Multiplexed I/O & Peripheral Pin PGOOD (General)
Design note: OpenDrainstatusoutput requiresexternalpullupresistor Thispinwill , . golowwhenVOUTisoutsidethedefinedpowergoodrange whenthe , dieishotterthanthethermalshutdownthreshold whenPVINisabove , theovervoltagethreshold orwhenPVINisbelowtheundervolt
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: LX7220-03ILQ-TR (MICROCHIP · VQFN-14(2x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
LX7220-03ILQ-TR (VQFN-14(2x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
LX7220-03ILQ-TR (VQFN-14(2x3)) - 2. Standard Pinout (Top View)
True package pinout (15 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
LX7220-03ILQ-TR (VQFN-14(2x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LX7220-03ILQ-TR (VQFN-14(2x3)) - 4. Package Dimensions (D×E×A)
VQFN-14(2x3) · 2.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
LX7220-03ILQ-TR (VQFN-14(2x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (15 Pads)Expand ›
6. Application SchematicSCHEMATIC
LX7220-03ILQ-TR (VQFN-14(2x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for LX7220
P19 · p19_fig01EXACT PACKAGE
LX7220-03ILQ-TR (VQFN-14(2x3)) — Land Pattern Recommendation
Land Pattern Recommendation
P1 · p01_fig011842×629px
LX7220-03ILQ-TR (VQFN-14(2x3)) — Figure 1: Typical 5V to 0.95V at 6A schematic
Figure 1: Typical 5V to 0.95V at 6A schematic
P1 · p01_fig01P1
LX7220-03ILQ-TR (VQFN-14(2x3)) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P2 · p02_fig011436×746px
LX7220-03ILQ-TR (VQFN-14(2x3)) — Figure 4: Pinout Ordering Information Temperature Package
Figure 4: Pinout Ordering Information Temperature Package
P18 · p18_fig012054×1890px
LX7220-03ILQ-TR (VQFN-14(2x3)) — Package Dimensions
Package Dimensions
P18 · p18_fig021982×827px
LX7220-03ILQ-TR (VQFN-14(2x3)) — X xy Output Voltage
X xy Output Voltage
P18 · p18_fig01P18
LX7220-03ILQ-TR (VQFN-14(2x3)) — Datasheet Page 18 (p18_fig01)
Datasheet Page 18 (p18_fig01)
P19 · p19_fig021530×311px
LX7220-03ILQ-TR (VQFN-14(2x3)) — PRODUCTION DATA -— Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing d
PRODUCTION DATA -— Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing d
P19 · p19_fig01P19
LX7220-03ILQ-TR (VQFN-14(2x3)) — Datasheet Page 19 (p19_fig01)
Datasheet Page 19 (p19_fig01)

Technical Specifications & Part Details (LX7220-03ILQ-TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:LX7220-03ILQ-TR (VQFN-14(2x3)) is a 14-pin standard electronic & interconnect component featuring a 3.00 × 2.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.7V to 5.5V supply operation across -40°C to +85°C with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1.2 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 2.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (VQFN-14(2x3))
Pin Count & Lead PitchN / e
14 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol15 auto-grouped pins
OK
IPC-7351B Land Pattern15 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VQFN-14(2x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 2.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.20 × 0.50 mm
Pins / Total PadsTopology
15P / 15Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
VQFN-14(2x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — LX7220-03ILQ-TR (VQFN-14(2x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of LX7220-03ILQ-TR (VQFN-14(2x3))?

Manufactured by MICROCHIP, the LX7220-03ILQ-TR is housed in a VQFN-14(2x3) package with 15 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.7V to 5.5V. Key pins include: 1 (PGOOD: Multiplexed I/O & Peripheral Pin PGOOD (General)), 2 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)), 3 (GND: Ground Reference Pin (GND)), 4 (SW: Multiplexed I/O & Peripheral Pin SW (General)), 5 (VIN: Power Supply Input (VIN — 2.7V to 5.5V)), 6 (VIN: Power Supply Input (VIN — 2.7V to 5.5V)).

What are the IPC-7351B PCB Footprint dimensions for LX7220-03ILQ-TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), LX7220-03ILQ-TR (VQFN-14(2x3)) has a nominal body envelope of 2.00 × 3.00 mm, pitch e = 0.50 mm, and 15 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for LX7220-03ILQ-TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for LX7220-03ILQ-TR (MICROCHIP, VQFN-14(2x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (15 pins) & LX7220 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PGOODDigital_IOSignal terminal PGOOD (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: PGOOD. Supported peripheral buses: General.
2SDADigital_IOSignal terminal SDA (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4SWDigital_IOSignal terminal SW (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
5VINPower_InPrimary positive power supply input (VIN) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
6VINPower_InPrimary positive power supply input (VIN) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
7VINPower_InPrimary positive power supply input (VIN) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
8VINPower_InPrimary positive power supply input (VIN) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
9SWDigital_IOSignal terminal SW (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General.
10ENDigital_IOChip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset.
11AGNDGND0V electrical ground return terminal (AGND) for internal core logic, I/O drivers, and analog sub-blocks.
12VOUTPower_OutRegulated power output rail (VOUT) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
13SCLDigital_IOSignal terminal SCL (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
14AVINPower_InPrimary positive power supply input (AVIN) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
15GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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