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MCP3918A1-E/SS (SSOP-20-208mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

MCP3918A1-E/SS

MICROCHIPID: C184945SSOP-20-208mil · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · MCP3918A1-E/SS (SSOP-20-208mil)1RESET/OSR02DV DD3AV DD4CH0+5CH0 -6NC7NC8A GND9REFIN+/OUT10REFIN -20SDI/OSR119SDO18SCK/MCLK17CS/BOOST16OSC2/MODE15OSC1/CLKI/GA14DR/GAIN113MDAT012NC11D GNDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=5.30mm · Pitch e=0.65mmD=7.20mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 5.30mm × 7.20mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RESET/OSR0ISystem Enable & Hardware Reset (RESET/OSR0)
2DV DDI/OMultiplexed I/O & Peripheral Pin DV DD (General)
3AV DDI/OMultiplexed I/O & Peripheral Pin AV DD (General)
4CH0+I/OMultiplexed I/O & Peripheral Pin CH0+ (General)
5CH0 -I/OMultiplexed I/O & Peripheral Pin CH0 - (General)
6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
7NCI/OMultiplexed I/O & Peripheral Pin NC (General)
8A GNDGNDGround Reference Pin (A GND)
9REFIN+/OUTI/OMultiplexed I/O & Peripheral Pin REFIN+/OUT (General)
10REFIN -I/OMultiplexed I/O & Peripheral Pin REFIN - (General)
11D GNDGNDGround Reference Pin (D GND)
12NCI/OMultiplexed I/O & Peripheral Pin NC (General)
13MDAT0I/OMultiplexed I/O & Peripheral Pin MDAT0 (General)
14DR/GAIN1AnalogMultiplexed I/O & Peripheral Pin DR/GAIN1 (General)
15OSC1/CLKI/GAIN0I/OMultiplexed I/O & Peripheral Pin OSC1/CLKI/GAIN0 (RTC/CLK)
16OSC2/MODEI/OMultiplexed I/O & Peripheral Pin OSC2/MODE (RTC/CLK)
17CS/BOOSTI/OMultiplexed I/O & Peripheral Pin CS/BOOST (General)
18SCK/MCLKI/OMultiplexed I/O & Peripheral Pin SCK/MCLK (SPI)
19SDOI/OMultiplexed I/O & Peripheral Pin SDO (General)
20SDI/OSR1I/OMultiplexed I/O & Peripheral Pin SDI/OSR1 (General)
PIN 1 RESET/OSR0
I
System Enable & Hardware Reset (RESET/OSR0)
Design note: MasterResetLogicInputPinorOSR0LogicInputPin
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: MCP3918A1-E/SS (MICROCHIP · SSOP-20-208mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
MCP3918A1-E/SS (SSOP-20-208mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
MCP3918A1-E/SS (SSOP-20-208mil) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
MCP3918A1-E/SS (SSOP-20-208mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
MCP3918A1-E/SS (SSOP-20-208mil) - 4. Package Dimensions (D×E×A)
SSOP-20-208mil · 5.30×7.20mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
MCP3918A1-E/SS (SSOP-20-208mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
MCP3918A1-E/SS (SSOP-20-208mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for MCP3918
P1 · p01_fig01377×200px
MCP3918A1-E/SS (SSOP-20-208mil) — 3V Single-Channel Analog Front End
3V Single-Channel Analog Front End
P2 · p02_fig011725×1158px
MCP3918A1-E/SS (SSOP-20-208mil) — Functional Block Diagram
Functional Block Diagram
P2 · p02_fig021777×936px
MCP3918A1-E/SS (SSOP-20-208mil) — REFIN+/OUT
REFIN+/OUT
P2 · p02_fig03456×247px
MCP3918A1-E/SS (SSOP-20-208mil) — -
-
P2 · p02_fig04159×348px
MCP3918A1-E/SS (SSOP-20-208mil) — EN_MDAT
EN_MDAT
P2 · p02_fig03P2
MCP3918A1-E/SS (SSOP-20-208mil) — Datasheet Page 2 (p02_fig03)
Datasheet Page 2 (p02_fig03)
P55 · p55_fig011777×635px
MCP3918A1-E/SS (SSOP-20-208mil) — FIGURE 7-1: MCP3918 2-Wire Interface Typical Application Schematic.
FIGURE 7-1: MCP3918 2-Wire Interface Typical Application Schematic.
P55 · p55_fig02586×398px
MCP3918A1-E/SS (SSOP-20-208mil) — FIGURE 7-1: MCP3918 2-Wire Interface Typical Application Schematic.
FIGURE 7-1: MCP3918 2-Wire Interface Typical Application Schematic.
P57 · p57_fig011777×1142px
MCP3918A1-E/SS (SSOP-20-208mil) — FIGURE 7-2: Frame Word. TABLE 7-4: FRAME COUNTER SETTINGS CNT1 CNT0 FRAME NUMBER
FIGURE 7-2: Frame Word. TABLE 7-4: FRAME COUNTER SETTINGS CNT1 CNT0 FRAME NUMBER
P57 · p57_fig021781×737px
MCP3918A1-E/SS (SSOP-20-208mil) — FIGURE 7-3: MCP3918 2-Wire Communication Protocol.
FIGURE 7-3: MCP3918 2-Wire Communication Protocol.
P59 · p59_fig011600×860px
MCP3918A1-E/SS (SSOP-20-208mil) — FIGURE 8-1: MCP3918 Three-Phase Shunt Energy Meter - Typical Application Schematic for Each Phase. 8.1 Power Supply Design and Bypassing
FIGURE 8-1: MCP3918 Three-Phase Shunt Energy Meter - Typical Application Schematic for Each Phase. 8.1 Power Supply Design and Bypassing
P59 · p59_fig01P59
MCP3918A1-E/SS (SSOP-20-208mil) — Datasheet Page 59 (p59_fig01)
Datasheet Page 59 (p59_fig01)
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (MCP3918A1-E/SS)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:MCP3918A1-E/SS (SSOP-20-208mil) is a 20-pin standard electronic & interconnect component featuring a 7.20 × 5.30 × 1.85 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 2.7V – 3.6V supply operation across -40°C to +125°C with integrated SPI, ADC, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V – 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
4 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.20 × 5.30 × 1.85 mm (A1=0.15 mm)
Package family: TSSOP (SSOP-20-208mil)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, ADC, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SSOP-20-208mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.20 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=1.85mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.60 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SSOP-20-208mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MCP3918A1-E/SS (SSOP-20-208mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MCP3918A1-E/SS (SSOP-20-208mil)?

Manufactured by MICROCHIP, the MCP3918A1-E/SS is housed in a SSOP-20-208mil package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 2.7V – 3.6V. Key pins include: 1 (RESET/OSR0: System Enable & Hardware Reset (RESET/OSR0)), 2 (DV DD: Multiplexed I/O & Peripheral Pin DV DD (General)), 3 (AV DD: Multiplexed I/O & Peripheral Pin AV DD (General)), 4 (CH0+: Multiplexed I/O & Peripheral Pin CH0+ (General)), 5 (CH0 -: Multiplexed I/O & Peripheral Pin CH0 - (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for MCP3918A1-E/SS?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP3918A1-E/SS (SSOP-20-208mil) has a nominal body envelope of 5.30 × 7.20 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP3918A1-E/SS?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP3918A1-E/SS (MICROCHIP, SSOP-20-208mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & MCP3918 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RESET/OSR0Digital_IOActive-low hardware reset terminal (RESET/OSR0): pulling this pin Low resets the processor core and peripherals.
2DV DDDigital_IOSignal terminal DV DD (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: DV DD. Supported peripheral buses: General.
3AV DDDigital_IOSignal terminal AV DD (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: AV DD. Supported peripheral buses: General.
4CH0+Digital_IOSignal terminal CH0+ (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: CH0+. Supported peripheral buses: General.
5CH0 -Digital_IOSignal terminal CH0 - (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: CH0 -. Supported peripheral buses: General.
6NCNCSignal terminal NC (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7NCNCSignal terminal NC (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
8A GNDGND0V electrical ground return terminal (A GND) for internal core logic, I/O drivers, and analog sub-blocks.
9REFIN+/OUTDigital_IOSignal terminal REFIN+/OUT (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: REFIN+/OUT. Supported peripheral buses: General.
10REFIN -Digital_IOSignal terminal REFIN - (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: REFIN -. Supported peripheral buses: General.
11D GNDGND0V electrical ground return terminal (D GND) for internal core logic, I/O drivers, and analog sub-blocks.
12NCNCSignal terminal NC (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13MDAT0Digital_IOSignal terminal MDAT0 (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: MDAT0. Supported peripheral buses: General.
14DR/GAIN1AnalogSignal terminal DR/GAIN1 (Analog, 2.7V – 3.6V domain). Multiplexed alternate functions: DR/GAIN1. Supported peripheral buses: General.
15OSC1/CLKI/GAIN0AnalogSignal terminal OSC1/CLKI/GAIN0 (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: OSC1/CLKI/GAIN0. Supported peripheral buses: RTC/CLK.
16OSC2/MODEDigital_IOSignal terminal OSC2/MODE (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: OSC2/MODE. Supported peripheral buses: RTC/CLK.
17CS/BOOSTDigital_IOSignal terminal CS/BOOST (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: CS/BOOST. Supported peripheral buses: General.
18SCK/MCLKDigital_IOSignal terminal SCK/MCLK (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: SCK/MCLK. Supported peripheral buses: SPI.
19SDODigital_IOSignal terminal SDO (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: SDO. Supported peripheral buses: General.
20SDI/OSR1Digital_IOSignal terminal SDI/OSR1 (I/O, 2.7V – 3.6V domain). Multiplexed alternate functions: SDI/OSR1. Supported peripheral buses: General.
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