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PIC16F84-04/P (PDIP-18) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC16F84-04/P

MICROCHIPID: C184831PDIP-18 · 18 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC16F84-04/P (PDIP-18)1RA22RA33RA4/T0CKI4MCLR#5VSS6RB0/INT7RB18RB29RB318RA117RA016OSC1/CLKIN15OSC2/CLKOUT14VDD13RB712RB611RB510RB4Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
123456789101112131415161718E=6.35mm · Pitch e=2.54mmD=22.32mm-10-8-6-4-202468101715131197531-1-3-5-7-9-11-13-15-17mm
3. 3D CAD MODEL
Package Body: 6.35mm × 22.32mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (18/18)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RA2I/OMultiplexed I/O & Peripheral Pin RA2 (General)
2RA3I/OMultiplexed I/O & Peripheral Pin RA3 (General)
3RA4/T0CKII/OMultiplexed I/O & Peripheral Pin RA4/T0CKI (General)
4MCLR#I/OMultiplexed I/O & Peripheral Pin MCLR# (General)
5VSSGNDGround Reference Pin (VSS)
6RB0/INTI/OMultiplexed I/O & Peripheral Pin RB0/INT (General)
7RB1I/OMultiplexed I/O & Peripheral Pin RB1 (General)
8RB2I/OMultiplexed I/O & Peripheral Pin RB2 (General)
9RB3I/OMultiplexed I/O & Peripheral Pin RB3 (General)
10RB4I/OMultiplexed I/O & Peripheral Pin RB4 (General)
11RB5I/OMultiplexed I/O & Peripheral Pin RB5 (General)
12RB6I/OMultiplexed I/O & Peripheral Pin RB6 (General)
13RB7I/OMultiplexed I/O & Peripheral Pin RB7 (General)
14VDDPowerPower Supply Input (VDD — 2.0V to 6.0V)
15OSC2/CLKOUTI/OMultiplexed I/O & Peripheral Pin OSC2/CLKOUT (RTC/CLK)
16OSC1/CLKINI/OMultiplexed I/O & Peripheral Pin OSC1/CLKIN (RTC/CLK)
17RA0I/OMultiplexed I/O & Peripheral Pin RA0 (General)
18RA1I/OMultiplexed I/O & Peripheral Pin RA1 (General)
PIN 1 RA2
I/O
Multiplexed I/O & Peripheral Pin RA2 (General)
Design note: Signal terminal RA2 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC16F84-04/P (MICROCHIP · PDIP-18)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC16F84-04/P (PDIP-18) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC16F84-04/P (PDIP-18) - 2. Standard Pinout (Top View)
True package pinout (18 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC16F84-04/P (PDIP-18) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC16F84-04/P (PDIP-18) - 4. Package Dimensions (D×E×A)
PDIP-18 · 6.35×22.32mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC16F84-04/P (PDIP-18) - 5. Recommended Land Pattern
IPC-7351B Footprint (18 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC16F84-04/P (PDIP-18) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for PIC16F84
P1 · p01_fig01867×698px
PIC16F84-04/P (PDIP-18) — PIC16F83 512 Flash 36 64 10
PIC16F83 512 Flash 36 64 10
P8 · p08_fig011777×1486px
PIC16F84-04/P (PDIP-18) — FIGURE 3-1: PIC16F8X BLOCK DIAGRAM
FIGURE 3-1: PIC16F8X BLOCK DIAGRAM
P27 · p27_fig011686×506px
PIC16F84-04/P (PDIP-18) — FIGURE 6-1: TMR0 BLOCK DIAGRAM
FIGURE 6-1: TMR0 BLOCK DIAGRAM
P27 · p27_fig021818×554px
PIC16F84-04/P (PDIP-18) — FIGURE 6-2: TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
FIGURE 6-2: TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
P53 · p53_fig011778×802px
PIC16F84-04/P (PDIP-18) — FIGURE 8-20: TYPICAL IN-SYSTEM SERIAL PROGRAMMING CONNECTION
FIGURE 8-20: TYPICAL IN-SYSTEM SERIAL PROGRAMMING CONNECTION
P53 · p53_fig01P53
PIC16F84-04/P (PDIP-18) — Datasheet Page 53 (p53_fig01)
Datasheet Page 53 (p53_fig01)
P112 · p112_fig011522×1922px
PIC16F84-04/P (PDIP-18) — (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
P112 · p112_fig01P112
PIC16F84-04/P (PDIP-18) — Datasheet Page 112 (p112_fig01)
Datasheet Page 112 (p112_fig01)
P113 · p113_fig011521×1922px
PIC16F84-04/P (PDIP-18) — (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
P111 · p111_fig01All Packages in PDF
PIC16F84-04/P (PDIP-18) — 18L SOIC
18L SOIC
P111 · p111_fig02All Packages in PDF
PIC16F84-04/P (PDIP-18) — AABBCDE XXXXXXXXXXXX XXXXXXXXXXXX | 18L SOIC | XXXXXXXXXXXX | 9648SAN /SO PIC16F84-04 | Example
AABBCDE XXXXXXXXXXXX XXXXXXXXXXXX | 18L SOIC | XXXXXXXXXXXX | 9648SAN /SO PIC16F84-04 | Example

Technical Specifications & Part Details (PIC16F84-04/P)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC16F84-04/P (PDIP-18) is a 18-pin standard electronic & interconnect component featuring a 22.32 × 6.35 × 3.50 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 2.0V to 6.0V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.0V to 6.0V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
10 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
22.32 × 6.35 × 3.50 mm (A1=0.51 mm)
Package family: DIP (PDIP-18)
Pin Count & Lead PitchN / e
18 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol18 auto-grouped pins
OK
IPC-7351B Land Pattern18 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-18)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
22.32 × 6.35 mm
Height (A) & Pitch (e)IPC-7351B
A=3.50mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
18P / 18Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PDIP-18
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16F84-04/P (PDIP-18)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16F84-04/P (PDIP-18)?

Manufactured by MICROCHIP, the PIC16F84-04/P is housed in a PDIP-18 package with 18 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 2.0V to 6.0V. Key pins include: 1 (RA2: Multiplexed I/O & Peripheral Pin RA2 (General)), 2 (RA3: Multiplexed I/O & Peripheral Pin RA3 (General)), 3 (RA4/T0CKI: Multiplexed I/O & Peripheral Pin RA4/T0CKI (General)), 4 (MCLR#: Multiplexed I/O & Peripheral Pin MCLR# (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RB0/INT: Multiplexed I/O & Peripheral Pin RB0/INT (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16F84-04/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F84-04/P (PDIP-18) has a nominal body envelope of 6.35 × 22.32 mm, pitch e = 2.54 mm, and 18 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F84-04/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F84-04/P (MICROCHIP, PDIP-18) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (18 pins) & PIC16F84 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RA2Digital_IOSignal terminal RA2 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
2RA3Digital_IOSignal terminal RA3 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RA3. Supported peripheral buses: General.
3RA4/T0CKIDigital_IOSignal terminal RA4/T0CKI (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RA4/T0CKI. Supported peripheral buses: General.
4MCLR#Digital_IOSignal terminal MCLR# (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General.
5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6RB0/INTDigital_IOSignal terminal RB0/INT (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RB0/INT. Supported peripheral buses: General.
7RB1Digital_IOSignal terminal RB1 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RB1. Supported peripheral buses: General.
8RB2Digital_IOSignal terminal RB2 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RB2. Supported peripheral buses: General.
9RB3Digital_IOSignal terminal RB3 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RB3. Supported peripheral buses: General.
10RB4Digital_IOSignal terminal RB4 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
11RB5Digital_IOSignal terminal RB5 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
12RB6Digital_IOSignal terminal RB6 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RB6. Supported peripheral buses: General.
13RB7Digital_IOSignal terminal RB7 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RB7. Supported peripheral buses: General.
14VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V to 6.0V domain (Max rating: 6.0V).
15OSC2/CLKOUTDigital_IOSignal terminal OSC2/CLKOUT (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: OSC2/CLKOUT. Supported peripheral buses: RTC/CLK.
16OSC1/CLKINDigital_IOSignal terminal OSC1/CLKIN (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: OSC1/CLKIN. Supported peripheral buses: RTC/CLK.
17RA0Digital_IOSignal terminal RA0 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RA0. Supported peripheral buses: General.
18RA1Digital_IOSignal terminal RA1 (I/O, 2.0V to 6.0V domain). Multiplexed alternate functions: RA1. Supported peripheral buses: General.
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