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MIC58P01YV (PLCC-28(11.5x11.5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

MIC58P01YV

MICROCHIPID: C184733PLCC-28(11.5x11.5) · 28 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · MIC58P01YV (PLCC-28(11.5x11.5))1CLEAR2NC3STROBE4NC5IN16IN27IN38IN49IN510IN611IN712IN813NC14NC28#OE/REST27VDD26NC25OUT124OUT223OUT322OUT421OUT520OUT619OUT718OUT817COM16NC15GNDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728E=11.50mm · Pitch e=1.27mmD=11.50mm-10-8-6-4-202468101086420-2-4-6-8-10mm
3. 3D CAD MODEL
Package Body: 11.50mm × 11.50mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1CLEARI/OMultiplexed I/O & Peripheral Pin CLEAR (General)
2NCI/OMultiplexed I/O & Peripheral Pin NC (General)
3STROBEI/OMultiplexed I/O & Peripheral Pin STROBE (General)
4NCI/OMultiplexed I/O & Peripheral Pin NC (General)
5IN1I/OMultiplexed I/O & Peripheral Pin IN1 (General)
6IN2I/OMultiplexed I/O & Peripheral Pin IN2 (General)
7IN3I/OMultiplexed I/O & Peripheral Pin IN3 (General)
8IN4I/OMultiplexed I/O & Peripheral Pin IN4 (General)
9IN5I/OMultiplexed I/O & Peripheral Pin IN5 (General)
10IN6I/OMultiplexed I/O & Peripheral Pin IN6 (General)
11IN7I/OMultiplexed I/O & Peripheral Pin IN7 (General)
12IN8I/OMultiplexed I/O & Peripheral Pin IN8 (General)
13NCI/OMultiplexed I/O & Peripheral Pin NC (General)
14NCI/OMultiplexed I/O & Peripheral Pin NC (General)
15GNDGNDGround Reference Pin (GND)
16NCI/OMultiplexed I/O & Peripheral Pin NC (General)
17COMI/OMultiplexed I/O & Peripheral Pin COM (General)
18OUT8I/OMultiplexed I/O & Peripheral Pin OUT8 (General)
19OUT7I/OMultiplexed I/O & Peripheral Pin OUT7 (General)
20OUT6I/OMultiplexed I/O & Peripheral Pin OUT6 (General)
21OUT5I/OMultiplexed I/O & Peripheral Pin OUT5 (General)
22OUT4I/OMultiplexed I/O & Peripheral Pin OUT4 (General)
23OUT3I/OMultiplexed I/O & Peripheral Pin OUT3 (General)
24OUT2I/OMultiplexed I/O & Peripheral Pin OUT2 (General)
25OUT1I/OMultiplexed I/O & Peripheral Pin OUT1 (General)
26NCI/OMultiplexed I/O & Peripheral Pin NC (General)
27VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
28#OE/RESTI/OMultiplexed I/O & Peripheral Pin #OE/REST (General)
PIN 1 CLEAR
I/O
Multiplexed I/O & Peripheral Pin CLEAR (General)
Design note: Signal terminal CLEAR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLEAR. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: MIC58P01YV (MICROCHIP · PLCC-28(11.5x11.5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
MIC58P01YV (PLCC-28(11.5x11.5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
MIC58P01YV (PLCC-28(11.5x11.5)) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
MIC58P01YV (PLCC-28(11.5x11.5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
MIC58P01YV (PLCC-28(11.5x11.5)) - 4. Package Dimensions (D×E×A)
PLCC-28(11.5x11.5) · 11.50×11.50mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
MIC58P01YV (PLCC-28(11.5x11.5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
MIC58P01YV (PLCC-28(11.5x11.5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for MIC58P01YV
P2 · p02_fig01EXACT PACKAGE
MIC58P01YV (PLCC-28(11.5x11.5)) — 28-Pin PLLC (V) (Top View)
28-Pin PLLC (V) (Top View)
P2 · p02_fig02EXACT PACKAGE
MIC58P01YV (PLCC-28(11.5x11.5)) — 24-Pin SOIC (WM) (not pin compatible with MIC5801YWM)
24-Pin SOIC (WM) (not pin compatible with MIC5801YWM)
P10 · p10_fig01EXACT PACKAGE
MIC58P01YV (PLCC-28(11.5x11.5)) — 28-Pin PLCC (V)
28-Pin PLCC (V)
P1 · p01_fig01724×395px
MIC58P01YV (PLCC-28(11.5x11.5)) — Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
P2 · p02_fig01P2
MIC58P01YV (PLCC-28(11.5x11.5)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig01516×430px
MIC58P01YV (PLCC-28(11.5x11.5)) — Micrel, Inc. MIC58P01 Typical Input
Micrel, Inc. MIC58P01 Typical Input
P8 · p08_fig011114×926px
MIC58P01YV (PLCC-28(11.5x11.5)) — Micrel, Inc. MIC58P01 Typical Application Schematic
Micrel, Inc. MIC58P01 Typical Application Schematic
P10 · p10_fig01P10
MIC58P01YV (PLCC-28(11.5x11.5)) — Datasheet Page 10 (p10_fig01)
Datasheet Page 10 (p10_fig01)
P9 · p09_fig01All Packages in PDF
MIC58P01YV (PLCC-28(11.5x11.5)) — 24-Pin Wide SOIC (WM)
24-Pin Wide SOIC (WM)

Technical Specifications & Part Details (MIC58P01YV)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:MIC58P01YV (PLCC-28(11.5x11.5)) is a 28-pin standard electronic & interconnect component featuring a 11.50 × 11.50 × 1.15 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 40°C to +85°C with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
5MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
11.50 × 11.50 × 1.15 mm (A1=0.03 mm)
Package family: LGA (PLCC-28(11.5x11.5))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PLCC-28(11.5x11.5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
11.50 × 11.50 mm
Height (A) & Pitch (e)IPC-7351B
A=1.15mm · e=1.27mm
Pad Size (W × L)Level B
0.76 × 2.03 mm
Pins / Total PadsTopology
28P / 28Pad (LGA_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PLCC-28(11.5x11.5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MIC58P01YV (PLCC-28(11.5x11.5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MIC58P01YV (PLCC-28(11.5x11.5))?

Manufactured by MICROCHIP, the MIC58P01YV is housed in a PLCC-28(11.5x11.5) package with 28 pins and a 1.27 mm lead pitch. Key pins include: 1 (CLEAR: Multiplexed I/O & Peripheral Pin CLEAR (General)), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (STROBE: Multiplexed I/O & Peripheral Pin STROBE (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (IN1: Multiplexed I/O & Peripheral Pin IN1 (General)), 6 (IN2: Multiplexed I/O & Peripheral Pin IN2 (General)).

What are the IPC-7351B PCB Footprint dimensions for MIC58P01YV?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC58P01YV (PLCC-28(11.5x11.5)) has a nominal body envelope of 11.50 × 11.50 mm, pitch e = 1.27 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC58P01YV?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC58P01YV (MICROCHIP, PLCC-28(11.5x11.5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & MIC58P01YV Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1CLEARDigital_IOSignal terminal CLEAR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLEAR. Supported peripheral buses: General.
2NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
3STROBEDigital_IOSignal terminal STROBE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: STROBE. Supported peripheral buses: General.
4NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
5IN1Digital_IOSignal terminal IN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN1. Supported peripheral buses: General.
6IN2Digital_IOSignal terminal IN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN2. Supported peripheral buses: General.
7IN3Digital_IOSignal terminal IN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN3. Supported peripheral buses: General.
8IN4Digital_IOSignal terminal IN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN4. Supported peripheral buses: General.
9IN5Digital_IOSignal terminal IN5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN5. Supported peripheral buses: General.
10IN6Digital_IOSignal terminal IN6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN6. Supported peripheral buses: General.
11IN7Digital_IOSignal terminal IN7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN7. Supported peripheral buses: General.
12IN8Digital_IOSignal terminal IN8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IN8. Supported peripheral buses: General.
13NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
15GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
16NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
17COMDigital_IOSignal terminal COM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: COM. Supported peripheral buses: General.
18OUT8Digital_IOSignal terminal OUT8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUT8. Supported peripheral buses: General.
19OUT7Digital_IOSignal terminal OUT7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUT7. Supported peripheral buses: General.
20OUT6Digital_IOSignal terminal OUT6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUT6. Supported peripheral buses: General.
21OUT5Digital_IOSignal terminal OUT5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUT5. Supported peripheral buses: General.
22OUT4Digital_IOSignal terminal OUT4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUT4. Supported peripheral buses: General.
23OUT3Digital_IOSignal terminal OUT3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUT3. Supported peripheral buses: General.
24OUT2Digital_IOSignal terminal OUT2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUT2. Supported peripheral buses: General.
25OUT1Digital_IOSignal terminal OUT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUT1. Supported peripheral buses: General.
26NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
27VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
28#OE/RESTDigital_IOSignal terminal #OE/REST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: #OE/REST. Supported peripheral buses: General.
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