Mechanical Dimensions & Land Pattern (TQFP-100(12x12))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
12.00 × 12.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.40mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit TQFP-100(12x12) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — PIC32MZ1024EFG100-I/PT (TQFP-100(12x12))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of PIC32MZ1024EFG100-I/PT (TQFP-100(12x12))?
Manufactured by MICROCHIP, the PIC32MZ1024EFG100-I/PT is housed in a TQFP-100(12x12) package with 100 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 2.1V to 3.6V. Key pins include: 1 (AERXERR: Multiplexed I/O & Peripheral Pin AERXERR (General)), 2 (EBIA5: Multiplexed I/O & Peripheral Pin EBIA5 (General)), 3 (EBID5: Multiplexed I/O & Peripheral Pin EBID5 (General)), 4 (EBID6: Multiplexed I/O & Peripheral Pin EBID6 (General)), 5 (EBID7: Multiplexed I/O & Peripheral Pin EBID7 (General)), 6 (EBIA6: Multiplexed I/O & Peripheral Pin EBIA6 (General)).
What are the IPC-7351B PCB Footprint dimensions for PIC32MZ1024EFG100-I/PT?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC32MZ1024EFG100-I/PT (TQFP-100(12x12)) has a nominal body envelope of 12.00 × 12.00 mm, pitch e = 0.40 mm, and 100 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC32MZ1024EFG100-I/PT?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC32MZ1024EFG100-I/PT (MICROCHIP, TQFP-100(12x12)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (100 pins) & PIC32MZ0512E / PIC32MZ1024E / PIC32MZ2048E Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | AERXERR | Digital_IO | Signal terminal AERXERR (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AERXERR. Supported peripheral buses: General. |
| 2 | EBIA5 | Digital_IO | Signal terminal EBIA5 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIA5. Supported peripheral buses: General. |
| 3 | EBID5 | Digital_IO | Signal terminal EBID5 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBID5. Supported peripheral buses: General. |
| 4 | EBID6 | Digital_IO | Signal terminal EBID6 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBID6. Supported peripheral buses: General. |
| 5 | EBID7 | Digital_IO | Signal terminal EBID7 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBID7. Supported peripheral buses: General. |
| 6 | EBIA6 | Digital_IO | Signal terminal EBIA6 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIA6. Supported peripheral buses: General. |
| 7 | EBIA12 | Digital_IO | Signal terminal EBIA12 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIA12. Supported peripheral buses: General. |
| 8 | EBIWE | Digital_IO | Signal terminal EBIWE (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIWE. Supported peripheral buses: General. |
| 9 | EBIOE | Digital_IO | Signal terminal EBIOE (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIOE. Supported peripheral buses: General. |
| 10 | ECOL | Digital_IO | Signal terminal ECOL (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: ECOL. Supported peripheral buses: General. |
| 11 | ECRS | Digital_IO | Signal terminal ECRS (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: ECRS. Supported peripheral buses: General. |
| 12 | AECRSDV | Digital_IO | Signal terminal AECRSDV (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AECRSDV. Supported peripheral buses: General. |
| 13 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 14 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 2.1V to 3.6V domain (Max rating: 3.6V). |
| 15 | MCLR | Digital_IO | Signal terminal MCLR (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: MCLR. Supported peripheral buses: General. |
| 16 | AEREFCLK | Digital_IO | Signal terminal AEREFCLK (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AEREFCLK. Supported peripheral buses: General. |
| 17 | TMS | Digital_IO | Signal terminal TMS (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: TMS. Supported peripheral buses: SWD/JTAG. |
| 18 | AERXD0 | Digital_IO | Signal terminal AERXD0 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AERXD0. Supported peripheral buses: General. |
| 19 | AERXD1 | Digital_IO | Signal terminal AERXD1 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AERXD1. Supported peripheral buses: General. |
| 20 | AN45 | Digital_IO | Signal terminal AN45 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AN45. Supported peripheral buses: General. |
| 21 | C1INB | Digital_IO | Signal terminal C1INB (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: C1INB. Supported peripheral buses: General. |
| 22 | C2INA | Digital_IO | Signal terminal C2INA (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: C2INA. Supported peripheral buses: General. |
| 23 | C2INB | Digital_IO | Signal terminal C2INB (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: C2INB. Supported peripheral buses: General. |
| 24 | PGEC1 | Digital_IO | Signal terminal PGEC1 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: PGEC1. Supported peripheral buses: General. |
| 25 | PGED1 | Digital_IO | Signal terminal PGED1 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: PGED1. Supported peripheral buses: General. |
| 26 | PGEC2 | Digital_IO | Signal terminal PGEC2 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: PGEC2. Supported peripheral buses: General. |
| 27 | PGED2 | Digital_IO | Signal terminal PGED2 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: PGED2. Supported peripheral buses: General. |
| 28 | VREF- | Analog | Signal terminal VREF- (Analog, 2.1V to 3.6V domain). Multiplexed alternate functions: VREF-. Supported peripheral buses: General. |
| 29 | VREF+ | Analog | Signal terminal VREF+ (Analog, 2.1V to 3.6V domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General. |
| 30 | AVDD | Power_In | Primary positive power supply input (AVDD) operating in the 2.1V to 3.6V domain (Max rating: 3.6V). |
| 31 | AVSS | GND | 0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 32 | EBIA10 | Digital_IO | Signal terminal EBIA10 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIA10. Supported peripheral buses: General. |
| 33 | EBIA7 | Digital_IO | Signal terminal EBIA7 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIA7. Supported peripheral buses: General. |
| 34 | EBIA13 | Digital_IO | Signal terminal EBIA13 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIA13. Supported peripheral buses: General. |
| 35 | AETXERR | Digital_IO | Signal terminal AETXERR (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AETXERR. Supported peripheral buses: General. |
| 36 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 37 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 2.1V to 3.6V domain (Max rating: 3.6V). |
| 38 | TCK | Digital_IO | Signal terminal TCK (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: TCK. Supported peripheral buses: SWD/JTAG. |
| 39 | TDI | Digital_IO | Signal terminal TDI (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: TDI. Supported peripheral buses: SWD/JTAG. |
| 40 | TDO | Digital_IO | Signal terminal TDO (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: TDO. Supported peripheral buses: SWD/JTAG. |
| 41 | AECRS | Digital_IO | Signal terminal AECRS (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AECRS. Supported peripheral buses: General. |
| 42 | AECOL | Digital_IO | Signal terminal AECOL (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AECOL. Supported peripheral buses: General. |
| 43 | AETXD3 | Digital_IO | Signal terminal AETXD3 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AETXD3. Supported peripheral buses: General. |
| 44 | AETXD2 | Digital_IO | Signal terminal AETXD2 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AETXD2. Supported peripheral buses: General. |
| 45 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 46 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 2.1V to 3.6V domain (Max rating: 3.6V). |
| 47 | AETXD0 | Digital_IO | Signal terminal AETXD0 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AETXD0. Supported peripheral buses: General. |
| 48 | AETXD1 | Digital_IO | Signal terminal AETXD1 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: AETXD1. Supported peripheral buses: General. |
| 49 | RC12 | Digital_IO | Signal terminal RC12 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: RC12. Supported peripheral buses: General. |
| 50 | RC15 | Digital_IO | Signal terminal RC15 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: RC15. Supported peripheral buses: General. |
| 51 | VBUS | Power_In | Primary positive power supply input (VBUS) operating in the 2.1V to 3.6V domain (Max rating: 3.6V). |
| 52 | VUSB3V3 | Power_In | Primary positive power supply input (VUSB3V3) operating in the 2.1V to 3.6V domain (Max rating: 3.6V). |
| 53 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 54 | D - | Digital_IO | Signal terminal D - (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: D -. Supported peripheral buses: USB. |
| 55 | D+ | Digital_IO | Signal terminal D+ (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: D+. Supported peripheral buses: USB. |
| 56 | USBID | Digital_IO | Signal terminal USBID (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: USBID. Supported peripheral buses: USB. |
| 57 | EBIRDY3 | Digital_IO | Signal terminal EBIRDY3 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIRDY3. Supported peripheral buses: General. |
| 58 | EBIRDY2 | Digital_IO | Signal terminal EBIRDY2 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIRDY2. Supported peripheral buses: General. |
| 59 | EBICS0 | Digital_IO | Signal terminal EBICS0 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBICS0. Supported peripheral buses: General. |
| 60 | EBIRDY1 | Digital_IO | Signal terminal EBIRDY1 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIRDY1. Supported peripheral buses: General. |
| 61 | EBIA14 | Digital_IO | Signal terminal EBIA14 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIA14. Supported peripheral buses: General. |
| 62 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 2.1V to 3.6V domain (Max rating: 3.6V). |
| 63 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 64 | EBIA9 | Digital_IO | Signal terminal EBIA9 (I/O, 2.1V to 3.6V domain). Multiplexed alternate functions: EBIA9. Supported peripheral buses: General. |