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PIC16C65A-20I/P (PDIP-40) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC16C65A-20I/P

MICROCHIPID: C184664PDIP-40 · 40 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC16C65A-20I/P (PDIP-40)1MCLR/VPP2RA03RA14RA25RA36RA4/T0CKI7RA5/SS#8RE0/RD#9OSC1/CLKIN10OSC2/CLKOUT11VDD12VSS13OSC1/CLKIN14OSC2/CLKOUT15RC0/T1OSO/T116RC1/T1OSI/CC17RC2/CCP118RC3/SCK/SCL19RD0/PSP020VDD40RB739RB638RB537RB436RB335RB234RB133RB0/INT32VDD31VSS30RD7/PSP729RD6/PSP628RD5/PSP527RD4/PSP426RC7/RX/DT25RC6/TX/CK24RC5/SDO23RC4/SDI/SDA22RD3/PSP321RD2/PSP2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.830.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940E=14.10mm · Pitch e=2.54mmD=48.26mm-22-20-18-16-14-12-10-8-6-4-2024681012141618202238363432302826242220181614121086420-2-4-6-8-10-12-14-16-18-20-22-24-26-28-30-32-34-36-38mm
3. 3D CAD MODEL
Package Body: 14.10mm × 48.26mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (40/40)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1MCLR/VPPI/OMultiplexed I/O & Peripheral Pin MCLR/VPP (General)
2RA0I/OMultiplexed I/O & Peripheral Pin RA0 (General)
3RA1I/OMultiplexed I/O & Peripheral Pin RA1 (General)
4RA2I/OMultiplexed I/O & Peripheral Pin RA2 (General)
5RA3I/OMultiplexed I/O & Peripheral Pin RA3 (General)
6RA4/T0CKII/OMultiplexed I/O & Peripheral Pin RA4/T0CKI (General)
7RA5/SS#I/OMultiplexed I/O & Peripheral Pin RA5/SS# (General)
8RE0/RD#I/OMultiplexed I/O & Peripheral Pin RE0/RD# (General)
9OSC1/CLKINI/OMultiplexed I/O & Peripheral Pin OSC1/CLKIN (RTC/CLK)
10OSC2/CLKOUTI/OMultiplexed I/O & Peripheral Pin OSC2/CLKOUT (RTC/CLK)
11VDDPowerPower Supply Input (VDD — 2.5V to 6.0V)
12VSSGNDGround Reference Pin (VSS)
13OSC1/CLKINI/OMultiplexed I/O & Peripheral Pin OSC1/CLKIN (RTC/CLK)
14OSC2/CLKOUTI/OMultiplexed I/O & Peripheral Pin OSC2/CLKOUT (RTC/CLK)
15RC0/T1OSO/T1CKII/OMultiplexed I/O & Peripheral Pin RC0/T1OSO/T1CKI (General)
16RC1/T1OSI/CCP2I/OMultiplexed I/O & Peripheral Pin RC1/T1OSI/CCP2 (General)
17RC2/CCP1I/OMultiplexed I/O & Peripheral Pin RC2/CCP1 (General)
18RC3/SCK/SCLI/OMultiplexed I/O & Peripheral Pin RC3/SCK/SCL (SPI, I2C)
19RD0/PSP0I/OMultiplexed I/O & Peripheral Pin RD0/PSP0 (General)
20VDDPowerPower Supply Input (VDD — 2.5V to 6.0V)
21RD2/PSP2I/OMultiplexed I/O & Peripheral Pin RD2/PSP2 (General)
22RD3/PSP3I/OMultiplexed I/O & Peripheral Pin RD3/PSP3 (General)
23RC4/SDI/SDAI/OMultiplexed I/O & Peripheral Pin RC4/SDI/SDA (I2C)
24RC5/SDOI/OMultiplexed I/O & Peripheral Pin RC5/SDO (General)
25RC6/TX/CKI/OMultiplexed I/O & Peripheral Pin RC6/TX/CK (General)
26RC7/RX/DTI/OMultiplexed I/O & Peripheral Pin RC7/RX/DT (General)
27RD4/PSP4I/OMultiplexed I/O & Peripheral Pin RD4/PSP4 (General)
28RD5/PSP5I/OMultiplexed I/O & Peripheral Pin RD5/PSP5 (General)
29RD6/PSP6I/OMultiplexed I/O & Peripheral Pin RD6/PSP6 (General)
30RD7/PSP7I/OMultiplexed I/O & Peripheral Pin RD7/PSP7 (General)
31VSSGNDGround Reference Pin (VSS)
32VDDPowerPower Supply Input (VDD — 2.5V to 6.0V)
33RB0/INTI/OMultiplexed I/O & Peripheral Pin RB0/INT (General)
34RB1I/OMultiplexed I/O & Peripheral Pin RB1 (General)
35RB2I/OMultiplexed I/O & Peripheral Pin RB2 (General)
36RB3I/OMultiplexed I/O & Peripheral Pin RB3 (General)
37RB4I/OMultiplexed I/O & Peripheral Pin RB4 (General)
38RB5I/OMultiplexed I/O & Peripheral Pin RB5 (General)
39RB6I/OMultiplexed I/O & Peripheral Pin RB6 (General)
40RB7I/OMultiplexed I/O & Peripheral Pin RB7 (General)
PIN 1 MCLR/VPP
I/O
Multiplexed I/O & Peripheral Pin MCLR/VPP (General)
Design note: Master clear reset input or programming voltage input . This pin is an active low reset to the device.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC16C65A-20I/P (MICROCHIP · PDIP-40)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC16C65A-20I/P (PDIP-40) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC16C65A-20I/P (PDIP-40) - 2. Standard Pinout (Top View)
True package pinout (40 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC16C65A-20I/P (PDIP-40) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC16C65A-20I/P (PDIP-40) - 4. Package Dimensions (D×E×A)
PDIP-40 · 14.10×48.26mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC16C65A-20I/P (PDIP-40) - 5. Recommended Land Pattern
IPC-7351B Footprint (40 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC16C65A-20I/P (PDIP-40) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for PIC16C65A
P1 · p01_fig01340×189px
PIC16C65A-20I/P (PDIP-40) — 8-Bit CMOS Microcontrollers
8-Bit CMOS Microcontrollers
P2 · p02_fig021368×571px
PIC16C65A-20I/P (PDIP-40) — PDIP, Windowed CERDIP
PDIP, Windowed CERDIP
P2 · p02_fig031305×678px
PIC16C65A-20I/P (PDIP-40) — DS30234E-page 2  1997-2013 Microchip Technology Inc.
DS30234E-page 2  1997-2013 Microchip Technology Inc.
P11 · p11_fig011424×1626px
PIC16C65A-20I/P (PDIP-40) — FIGURE 3-2: PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM
FIGURE 3-2: PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM
P78 · p78_fig01728×492px
PIC16C65A-20I/P (PDIP-40) — FIGURE 10-2: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 10-2: CAPTURE MODE OPERATION BLOCK DIAGRAM
P79 · p79_fig01729×244px
PIC16C65A-20I/P (PDIP-40) — FIGURE 10-3: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 10-3: COMPARE MODE OPERATION BLOCK DIAGRAM
P79 · p79_fig02726×576px
PIC16C65A-20I/P (PDIP-40) — FIGURE 10-3: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 10-3: COMPARE MODE OPERATION BLOCK DIAGRAM
P87 · p87_fig011382×730px
PIC16C65A-20I/P (PDIP-40) — FIGURE 11-4: SPI MASTER/SLAVE CONNECTION
FIGURE 11-4: SPI MASTER/SLAVE CONNECTION
P92 · p92_fig011383×730px
PIC16C65A-20I/P (PDIP-40) — FIGURE 11-10: SPI MASTER/SLAVE CONNECTION (PIC16C66/67)
FIGURE 11-10: SPI MASTER/SLAVE CONNECTION (PIC16C66/67)
P142 · p142_fig011475×1233px
PIC16C65A-20I/P (PDIP-40) — FIGURE 13-22: WAKE-UP FROM SLEEP THROUGH INTERRUPT
FIGURE 13-22: WAKE-UP FROM SLEEP THROUGH INTERRUPT
P142 · p142_fig021475×768px
PIC16C65A-20I/P (PDIP-40) — FIGURE 13-23: TYPICAL IN-CIRCUIT SERIAL
FIGURE 13-23: TYPICAL IN-CIRCUIT SERIAL
P142 · p142_fig01P142
PIC16C65A-20I/P (PDIP-40) — Datasheet Page 142 (p142_fig01)
Datasheet Page 142 (p142_fig01)
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (PIC16C65A-20I/P)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC16C65A-20I/P (PDIP-40) is a 40-pin standard electronic & interconnect component featuring a 48.26 × 14.10 × 3.85 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 2.5V to 6.0V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.5V to 6.0V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
48.26 × 14.10 × 3.85 mm (A1=0.51 mm)
Package family: DIP (PDIP-40)
Pin Count & Lead PitchN / e
40 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol40 auto-grouped pins
OK
IPC-7351B Land Pattern40 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-40)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
48.26 × 14.10 mm
Height (A) & Pitch (e)IPC-7351B
A=3.85mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
40P / 40Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PDIP-40
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16C65A-20I/P (PDIP-40)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16C65A-20I/P (PDIP-40)?

Manufactured by MICROCHIP, the PIC16C65A-20I/P is housed in a PDIP-40 package with 40 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 2.5V to 6.0V. Key pins include: 1 (MCLR/VPP: Multiplexed I/O & Peripheral Pin MCLR/VPP (General)), 2 (RA0: Multiplexed I/O & Peripheral Pin RA0 (General)), 3 (RA1: Multiplexed I/O & Peripheral Pin RA1 (General)), 4 (RA2: Multiplexed I/O & Peripheral Pin RA2 (General)), 5 (RA3: Multiplexed I/O & Peripheral Pin RA3 (General)), 6 (RA4/T0CKI: Multiplexed I/O & Peripheral Pin RA4/T0CKI (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16C65A-20I/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16C65A-20I/P (PDIP-40) has a nominal body envelope of 14.10 × 48.26 mm, pitch e = 2.54 mm, and 40 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16C65A-20I/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16C65A-20I/P (MICROCHIP, PDIP-40) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (40 pins) & PIC16C65A Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1MCLR/VPPDigital_IOSignal terminal MCLR/VPP (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: MCLR/VPP. Supported peripheral buses: General.
2RA0Digital_IOSignal terminal RA0 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RA0. Supported peripheral buses: General.
3RA1Digital_IOSignal terminal RA1 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RA1. Supported peripheral buses: General.
4RA2Digital_IOSignal terminal RA2 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
5RA3Digital_IOSignal terminal RA3 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RA3. Supported peripheral buses: General.
6RA4/T0CKIDigital_IOSignal terminal RA4/T0CKI (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RA4/T0CKI. Supported peripheral buses: General.
7RA5/SS#Digital_IOSignal terminal RA5/SS# (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RA5/SS#. Supported peripheral buses: General.
8RE0/RD#Digital_IOSignal terminal RE0/RD# (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RE0/RD#. Supported peripheral buses: General.
9OSC1/CLKINDigital_IOSignal terminal OSC1/CLKIN (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: OSC1/CLKIN. Supported peripheral buses: RTC/CLK.
10OSC2/CLKOUTDigital_IOSignal terminal OSC2/CLKOUT (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: OSC2/CLKOUT. Supported peripheral buses: RTC/CLK.
11VDDPower_InPrimary positive power supply input (VDD) operating in the 2.5V to 6.0V domain (Max rating: 6.0V).
12VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
13OSC1/CLKINDigital_IOSignal terminal OSC1/CLKIN (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: OSC1/CLKIN. Supported peripheral buses: RTC/CLK.
14OSC2/CLKOUTDigital_IOSignal terminal OSC2/CLKOUT (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: OSC2/CLKOUT. Supported peripheral buses: RTC/CLK.
15RC0/T1OSO/T1CKIDigital_IOSignal terminal RC0/T1OSO/T1CKI (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RC0/T1OSO/T1CKI. Supported peripheral buses: General.
16RC1/T1OSI/CCP2Digital_IOSignal terminal RC1/T1OSI/CCP2 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RC1/T1OSI/CCP2. Supported peripheral buses: General.
17RC2/CCP1Digital_IOSignal terminal RC2/CCP1 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RC2/CCP1. Supported peripheral buses: General.
18RC3/SCK/SCLDigital_IOSignal terminal RC3/SCK/SCL (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RC3/SCK/SCL. Supported peripheral buses: SPI, I2C.
19RD0/PSP0Digital_IOSignal terminal RD0/PSP0 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RD0/PSP0. Supported peripheral buses: General.
20VDDPower_InPrimary positive power supply input (VDD) operating in the 2.5V to 6.0V domain (Max rating: 6.0V).
21RD2/PSP2Digital_IOSignal terminal RD2/PSP2 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RD2/PSP2. Supported peripheral buses: General.
22RD3/PSP3Digital_IOSignal terminal RD3/PSP3 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RD3/PSP3. Supported peripheral buses: General.
23RC4/SDI/SDADigital_IOSignal terminal RC4/SDI/SDA (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RC4/SDI/SDA. Supported peripheral buses: I2C.
24RC5/SDODigital_IOSignal terminal RC5/SDO (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RC5/SDO. Supported peripheral buses: General.
25RC6/TX/CKDigital_IOSignal terminal RC6/TX/CK (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RC6/TX/CK. Supported peripheral buses: General.
26RC7/RX/DTDigital_IOSignal terminal RC7/RX/DT (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RC7/RX/DT. Supported peripheral buses: General.
27RD4/PSP4Digital_IOSignal terminal RD4/PSP4 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RD4/PSP4. Supported peripheral buses: General.
28RD5/PSP5Digital_IOSignal terminal RD5/PSP5 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RD5/PSP5. Supported peripheral buses: General.
29RD6/PSP6Digital_IOSignal terminal RD6/PSP6 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RD6/PSP6. Supported peripheral buses: General.
30RD7/PSP7Digital_IOSignal terminal RD7/PSP7 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RD7/PSP7. Supported peripheral buses: General.
31VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32VDDPower_InPrimary positive power supply input (VDD) operating in the 2.5V to 6.0V domain (Max rating: 6.0V).
33RB0/INTDigital_IOSignal terminal RB0/INT (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RB0/INT. Supported peripheral buses: General.
34RB1Digital_IOSignal terminal RB1 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RB1. Supported peripheral buses: General.
35RB2Digital_IOSignal terminal RB2 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RB2. Supported peripheral buses: General.
36RB3Digital_IOSignal terminal RB3 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RB3. Supported peripheral buses: General.
37RB4Digital_IOSignal terminal RB4 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
38RB5Digital_IOSignal terminal RB5 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
39RB6Digital_IOSignal terminal RB6 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RB6. Supported peripheral buses: General.
40RB7Digital_IOSignal terminal RB7 (I/O, 2.5V to 6.0V domain). Multiplexed alternate functions: RB7. Supported peripheral buses: General.
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