SST39LF020-45-4C-WHE (TSOP-32-12.5mm) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of SST39LF020-45-4C-WHE (TSOP-32-12.5mm)?

Manufactured by MICROCHIP, the SST39LF020-45-4C-WHE is housed in a TSOP-32-12.5mm package with 32 pins and a 0.50 mm lead pitch. Key pins include: 1 (A11: Multiplexed I/O & Peripheral Pin A11 (General)), 2 (A9: Multiplexed I/O & Peripheral Pin A9 (General)), 3 (A8: Multiplexed I/O & Peripheral Pin A8 (General)), 4 (A13: Multiplexed I/O & Peripheral Pin A13 (General)), 5 (A14: Multiplexed I/O & Peripheral Pin A14 (General)), 6 (A17: Multiplexed I/O & Peripheral Pin A17 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for SST39LF020-45-4C-WHE?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SST39LF020-45-4C-WHE (TSOP-32-12.5mm) has a nominal body envelope of 12.40 × 8.00 mm, pitch e = 0.50 mm, and 32 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SST39LF020-45-4C-WHE?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SST39LF020-45-4C-WHE (MICROCHIP, TSOP-32-12.5mm) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 12.40mm × 8.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (32/32)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	A11	I/O	Multiplexed I/O & Peripheral Pin A11 (General)
2	A9	I/O	Multiplexed I/O & Peripheral Pin A9 (General)
3	A8	I/O	Multiplexed I/O & Peripheral Pin A8 (General)
4	A13	I/O	Multiplexed I/O & Peripheral Pin A13 (General)
5	A14	I/O	Multiplexed I/O & Peripheral Pin A14 (General)
6	A17	I/O	Multiplexed I/O & Peripheral Pin A17 (General)
7	WE#	I/O	Multiplexed I/O & Peripheral Pin WE# (General)
8	VDD	Power	Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)
9	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
10	Nov2008	I/O	Multiplexed I/O & Peripheral Pin Nov2008 (General)
11	Feb2009	I/O	Multiplexed I/O & Peripheral Pin Feb2009 (General)
12	Apr2009	I/O	Multiplexed I/O & Peripheral Pin Apr2009 (General)
13	Sep2009	I/O	Multiplexed I/O & Peripheral Pin Sep2009 (General)
14	Jan2010	I/O	Multiplexed I/O & Peripheral Pin Jan2010 (General)
15	A5	I/O	Multiplexed I/O & Peripheral Pin A5 (General)
16	A4	I/O	Multiplexed I/O & Peripheral Pin A4 (General)
17	A3	I/O	Multiplexed I/O & Peripheral Pin A3 (General)
18	A2	I/O	Multiplexed I/O & Peripheral Pin A2 (General)
19	A1	I/O	Multiplexed I/O & Peripheral Pin A1 (General)
20	A0	I/O	Multiplexed I/O & Peripheral Pin A0 (General)
21	DQ0	I/O	Multiplexed I/O & Peripheral Pin DQ0 (General)
22	DQ1	I/O	Multiplexed I/O & Peripheral Pin DQ1 (General)
23	DQ2	I/O	Multiplexed I/O & Peripheral Pin DQ2 (General)
24	VSS	GND	Ground Reference Pin (VSS)
25	DQ3	I/O	Multiplexed I/O & Peripheral Pin DQ3 (General)
26	DQ4	I/O	Multiplexed I/O & Peripheral Pin DQ4 (General)
27	DQ5	I/O	Multiplexed I/O & Peripheral Pin DQ5 (General)
28	DQ6	I/O	Multiplexed I/O & Peripheral Pin DQ6 (General)
29	DQ7	I/O	Multiplexed I/O & Peripheral Pin DQ7 (General)
30	CE#	I/O	Multiplexed I/O & Peripheral Pin CE# (General)
31	A10	I/O	Multiplexed I/O & Peripheral Pin A10 (General)
32	OE#	I/O	Multiplexed I/O & Peripheral Pin OE# (General)

PIN 1 A11

I/O

Multiplexed I/O & Peripheral Pin A11 (General)

Design note: Signal terminal A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A11. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

SST39LF020-45-4C-WHE (TSOP-32-12.5mm) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

SST39LF020-45-4C-WHE (TSOP-32-12.5mm) - 2. Standard Pinout (Top View)

True package pinout (32 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

SST39LF020-45-4C-WHE (TSOP-32-12.5mm) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

SST39LF020-45-4C-WHE (TSOP-32-12.5mm) - 4. Package Dimensions (D×E×A)

TSOP-32-12.5mm · 12.40×8.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

SST39LF020-45-4C-WHE (TSOP-32-12.5mm) - 5. Recommended Land Pattern

IPC-7351B Footprint (32 Pads)Expand ›

6. Application SchematicSCHEMATIC

SST39LF020-45-4C-WHE (TSOP-32-12.5mm) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)

Showing 1–11 of 11 uncropped original figures for SST39LF020

P1 · p01_fig01469×310px

A Microchip Technology Company HHH, ® A Microchip Technology Company

P2 · p02_fig01468×310px

Product Description

P4 · p04_fig01468×310px

Pin Assignments

P4 · p04_fig022037×1869px

Figure 2: Pin Assignments for 32-lead PLCC

P4 · p04_fig02P4

Datasheet Page 4 (p04_fig02)

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A Microchip Technology Company svete, ® A Microchip Technology Company

P6 · p06_fig022037×964px

SST39LF020-45-4C-WHE (TSOP-32-12.5mm) — Figure 5: Pin Assignment for 34-ball WFBGA (4mm x 6mm) for 1 Mbit and 2 Mbit Table 1: Pin Description Symbol Pin Name Functions AMS1-A0

Figure 5: Pin Assignment for 34-ball WFBGA (4mm x 6mm) for 1 Mbit and 2 Mbit Table 1: Pin Description Symbol Pin Name Functions AMS1-A0

P6 · p06_fig02P6

Datasheet Page 6 (p06_fig02)

P28 · p28_fig01468×310px

A Microchip Technology Company svete, ® A Microchip Technology Company

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Figure 23:32-lead Thin Small Outline Package (TSOP) 8mm x 14mm

P30 · p30_fig01468×310px

Table 14:Revision History

Technical Specifications & Part Details (SST39LF020-45-4C-WHE)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:SST39LF020-45-4C-WHE (TSOP-32-12.5mm) is a 32-pin standard electronic & interconnect component featuring a 8.00 × 12.40 × 2.45 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

14 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

8.00 × 12.40 × 2.45 mm (A1=0.20 mm)

Package family: SOP (TSOP-32-12.5mm)

Pin Count & Lead PitchN / e

32 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol32 auto-grouped pins

IPC-7351B Land Pattern32 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSOP-32-12.5mm)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

8.00 × 12.40 mm

Height (A) & Pitch (e)IPC-7351B

A=2.45mm · e=0.50mm

Pad Size (W × L)Level B

0.28 × 1.50 mm

Pins / Total PadsTopology

32P / 32Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TSOP-32-12.5mm	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — SST39LF020-45-4C-WHE (TSOP-32-12.5mm)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of SST39LF020-45-4C-WHE (TSOP-32-12.5mm)?

Manufactured by MICROCHIP, the SST39LF020-45-4C-WHE is housed in a TSOP-32-12.5mm package with 32 pins and a 0.50 mm lead pitch. Key pins include: 1 (A11: Multiplexed I/O & Peripheral Pin A11 (General)), 2 (A9: Multiplexed I/O & Peripheral Pin A9 (General)), 3 (A8: Multiplexed I/O & Peripheral Pin A8 (General)), 4 (A13: Multiplexed I/O & Peripheral Pin A13 (General)), 5 (A14: Multiplexed I/O & Peripheral Pin A14 (General)), 6 (A17: Multiplexed I/O & Peripheral Pin A17 (General)).

What are the IPC-7351B PCB Footprint dimensions for SST39LF020-45-4C-WHE?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SST39LF020-45-4C-WHE (TSOP-32-12.5mm) has a nominal body envelope of 12.40 × 8.00 mm, pitch e = 0.50 mm, and 32 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SST39LF020-45-4C-WHE?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SST39LF020-45-4C-WHE (MICROCHIP, TSOP-32-12.5mm) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (32 pins) & SST39LF020 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	A11	Digital_IO	Signal terminal A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A11. Supported peripheral buses: General.
2	A9	Digital_IO	Signal terminal A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A9. Supported peripheral buses: General.
3	A8	Digital_IO	Signal terminal A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A8. Supported peripheral buses: General.
4	A13	Digital_IO	Signal terminal A13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A13. Supported peripheral buses: General.
5	A14	Digital_IO	Signal terminal A14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A14. Supported peripheral buses: General.
6	A17	Digital_IO	Signal terminal A17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A17. Supported peripheral buses: General.
7	WE#	Digital_IO	Signal terminal WE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WE#. Supported peripheral buses: General.
8	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
10	Nov2008	Digital_IO	Signal terminal Nov2008 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Nov2008. Supported peripheral buses: General.
11	Feb2009	Digital_IO	Signal terminal Feb2009 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Feb2009. Supported peripheral buses: General.
12	Apr2009	Digital_IO	Signal terminal Apr2009 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Apr2009. Supported peripheral buses: General.
13	Sep2009	Digital_IO	Signal terminal Sep2009 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Sep2009. Supported peripheral buses: General.
14	Jan2010	Digital_IO	Signal terminal Jan2010 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Jan2010. Supported peripheral buses: General.
15	A5	Digital_IO	Signal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
16	A4	Digital_IO	Signal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
17	A3	Digital_IO	Signal terminal A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
18	A2	Digital_IO	Signal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
19	A1	Digital_IO	Signal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
20	A0	Digital_IO	Signal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
21	DQ0	Digital_IO	Signal terminal DQ0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ0. Supported peripheral buses: General.
22	DQ1	Digital_IO	Signal terminal DQ1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ1. Supported peripheral buses: General.
23	DQ2	Digital_IO	Signal terminal DQ2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ2. Supported peripheral buses: General.
24	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
25	DQ3	Digital_IO	Signal terminal DQ3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ3. Supported peripheral buses: General.
26	DQ4	Digital_IO	Signal terminal DQ4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ4. Supported peripheral buses: General.
27	DQ5	Digital_IO	Signal terminal DQ5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ5. Supported peripheral buses: General.
28	DQ6	Digital_IO	Signal terminal DQ6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ6. Supported peripheral buses: General.
29	DQ7	Digital_IO	Signal terminal DQ7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DQ7. Supported peripheral buses: General.
30	CE#	Digital_IO	Signal terminal CE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CE#. Supported peripheral buses: General.
31	A10	Digital_IO	Signal terminal A10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A10. Supported peripheral buses: General.
32	OE#	Digital_IO	Signal terminal OE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OE#. Supported peripheral buses: General.

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