PIC18F8527-I/PT (TQFP-80(12x12)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of PIC18F8527-I/PT (TQFP-80(12x12))?

Manufactured by MICROCHIP, the PIC18F8527-I/PT is housed in a TQFP-80(12x12) package with 80 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (RH2/A18: Multiplexed I/O & Peripheral Pin RH2/A18 (General)), 2 (RH3/A19: Multiplexed I/O & Peripheral Pin RH3/A19 (General)), 3 (RE1/AD9/WR#/P2C: Multiplexed I/O & Peripheral Pin RE1/AD9/WR#/P2C (General)), 4 (RE0/AD8/RD#/P2D: Multiplexed I/O & Peripheral Pin RE0/AD8/RD#/P2D (General)), 5 (RG0/ECCP3/P3A: Multiplexed I/O & Peripheral Pin RG0/ECCP3/P3A (General)), 6 (RG1/TX2/CK2: Multiplexed I/O & Peripheral Pin RG1/TX2/CK2 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for PIC18F8527-I/PT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F8527-I/PT (TQFP-80(12x12)) has a nominal body envelope of 12.00 × 12.00 mm, pitch e = 0.50 mm, and 80 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F8527-I/PT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F8527-I/PT (MICROCHIP, TQFP-80(12x12)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 12.00mm × 12.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (80/80)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	RH2/A18	I/O	Multiplexed I/O & Peripheral Pin RH2/A18 (General)
2	RH3/A19	I/O	Multiplexed I/O & Peripheral Pin RH3/A19 (General)
3	RE1/AD9/WR#/P2C	I/O	Multiplexed I/O & Peripheral Pin RE1/AD9/WR#/P2C (General)
4	RE0/AD8/RD#/P2D	I/O	Multiplexed I/O & Peripheral Pin RE0/AD8/RD#/P2D (General)
5	RG0/ECCP3/P3A	I/O	Multiplexed I/O & Peripheral Pin RG0/ECCP3/P3A (General)
6	RG1/TX2/CK2	I/O	Multiplexed I/O & Peripheral Pin RG1/TX2/CK2 (General)
7	NC	NC	No Connect (Leave Floating)
8	RG3/CCP4/P3D	I/O	Multiplexed I/O & Peripheral Pin RG3/CCP4/P3D (General)
9	IO4	I/O	GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10	RG4/CCP5/P1D	I/O	Multiplexed I/O & Peripheral Pin RG4/CCP5/P1D (General)
11	VSS	GND	Ground Reference Pin (VSS)
12	VDD	Power	Power Supply Input (VDD — 2.0V to 5.5V)
13	RF7/SS1@	I/O	Multiplexed I/O & Peripheral Pin RF7/SS1@ (General)
14	RF6/AN11	I/O	Multiplexed I/O & Peripheral Pin RF6/AN11 (General)
15	RF5/AN10/CVREF	I/O	Multiplexed I/O & Peripheral Pin RF5/AN10/CVREF (General)
16	RF4/AN9	I/O	Multiplexed I/O & Peripheral Pin RF4/AN9 (General)
17	RF3/AN8	I/O	Multiplexed I/O & Peripheral Pin RF3/AN8 (General)
18	RF2/AN7/C1OUT	I/O	Multiplexed I/O & Peripheral Pin RF2/AN7/C1OUT (General)
19	RH7/AN15/P1B(2)	I/O	Multiplexed I/O & Peripheral Pin RH7/AN15/P1B(2) (General)
20	RH6/AN14/P1C(2)	I/O	Multiplexed I/O & Peripheral Pin RH6/AN14/P1C(2) (General)
21	RH5/AN13/P3B(2)	I/O	Multiplexed I/O & Peripheral Pin RH5/AN13/P3B(2) (General)
22	RH4/AN12/P3C(2)	I/O	Multiplexed I/O & Peripheral Pin RH4/AN12/P3C(2) (General)
23	RF1/AN6/C2OUT	I/O	Multiplexed I/O & Peripheral Pin RF1/AN6/C2OUT (General)
24	RF0/AN5	I/O	Multiplexed I/O & Peripheral Pin RF0/AN5 (General)
25	AVDD	Power	Power Supply Input (AVDD — 2.0V to 5.5V)
26	AVSS	GND	Ground Reference Pin (AVSS)
27	RA3/AN3/VREF+	Analog	Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
28	RA2/AN2/VREF-	Analog	Multiplexed I/O & Peripheral Pin RA2/AN2/VREF- (General)
29	RA1/AN1	I/O	Multiplexed I/O & Peripheral Pin RA1/AN1 (General)
30	RA0/AN0	I/O	Multiplexed I/O & Peripheral Pin RA0/AN0 (General)
31	VSS	GND	Ground Reference Pin (VSS)
32	VDD	Power	Power Supply Input (VDD — 2.0V to 5.5V)
33	RA5/AN4/HLVDIN	I/O	Multiplexed I/O & Peripheral Pin RA5/AN4/HLVDIN (General)
34	RA4/T0CKI	I/O	Multiplexed I/O & Peripheral Pin RA4/T0CKI (General)
35	IO35	I/O	General Purpose Digital I/O Pin IO35
36	RC0/T1OSO/T13CKI	I/O	Multiplexed I/O & Peripheral Pin RC0/T1OSO/T13CKI (General)
37	RC6/TX1/CK1	I/O	Multiplexed I/O & Peripheral Pin RC6/TX1/CK1 (General)
38	RC7/RX1/DT1	I/O	Multiplexed I/O & Peripheral Pin RC7/RX1/DT1 (General)
39	IO39	I/O	General Purpose Digital I/O Pin IO39
40	IO40	I/O	General Purpose Digital I/O Pin IO40
41	RJ6/LB#	I/O	Multiplexed I/O & Peripheral Pin RJ6/LB# (General)
42	RJ7/UB#	I/O	Multiplexed I/O & Peripheral Pin RJ7/UB# (General)
43	RC2/ECCP1/P1A	I/O	Multiplexed I/O & Peripheral Pin RC2/ECCP1/P1A (General)
44	RC3/SCK1/SCL1	I/O	Multiplexed I/O & Peripheral Pin RC3/SCK1/SCL1 (SPI, I2C)
45	RC4/SDI1/SDA1	I/O	Multiplexed I/O & Peripheral Pin RC4/SDI1/SDA1 (I2C)
46	RC5/SDO1	I/O	Multiplexed I/O & Peripheral Pin RC5/SDO1 (General)
47	RB7/KBI3/PGD	I/O	Multiplexed I/O & Peripheral Pin RB7/KBI3/PGD (General)
48	VDD	Power	Power Supply Input (VDD — 2.0V to 5.5V)
49	IO49	I/O	General Purpose Digital I/O Pin IO49
50	IO50	I/O	General Purpose Digital I/O Pin IO50
51	VSS	GND	Ground Reference Pin (VSS)
52	RB6/KBI2/PGC	I/O	Multiplexed I/O & Peripheral Pin RB6/KBI2/PGC (General)
53	RB5/KBI1/PGM	I/O	Multiplexed I/O & Peripheral Pin RB5/KBI1/PGM (General)
54	RB4/KBI0	I/O	Multiplexed I/O & Peripheral Pin RB4/KBI0 (General)
55	IO55	I/O	General Purpose Digital I/O Pin IO55
56	RB2/INT2	I/O	Multiplexed I/O & Peripheral Pin RB2/INT2 (General)
57	RB1/INT1	I/O	Multiplexed I/O & Peripheral Pin RB1/INT1 (General)
58	RB0/INT0	I/O	Multiplexed I/O & Peripheral Pin RB0/INT0 (General)
59	RJ3/WRH#	I/O	Multiplexed I/O & Peripheral Pin RJ3/WRH# (General)
60	RJ2/WRL#	I/O	Multiplexed I/O & Peripheral Pin RJ2/WRL# (General)
61	RJ1/OE#	I/O	Multiplexed I/O & Peripheral Pin RJ1/OE# (General)
62	RJ0/ALE	I/O	Multiplexed I/O & Peripheral Pin RJ0/ALE (General)
63	RD7/AD7/PSP7/SS2#	I/O	Multiplexed I/O & Peripheral Pin RD7/AD7/PSP7/SS2# (General)
64	RD6/AD6/PSP6/SCK2/SCL2	I/O	Multiplexed I/O & Peripheral Pin RD6/AD6/PSP6/SCK2/SCL2 (SPI, I2C)
65	RD5/AD5/PSP5/SDI2/SDA2	I/O	Multiplexed I/O & Peripheral Pin RD5/AD5/PSP5/SDI2/SDA2 (I2C)
66	RD4/AD4/PSP4/SDO2	I/O	Multiplexed I/O & Peripheral Pin RD4/AD4/PSP4/SDO2 (General)
67	RD3/AD3/PSP3	I/O	Multiplexed I/O & Peripheral Pin RD3/AD3/PSP3 (General)
68	RD2/AD2/PSP2	I/O	Multiplexed I/O & Peripheral Pin RD2/AD2/PSP2 (General)
69	RD1/AD1/PSP1	I/O	Multiplexed I/O & Peripheral Pin RD1/AD1/PSP1 (General)
70	VSS	GND	Ground Reference Pin (VSS)
71	VDD	Power	Power Supply Input (VDD — 2.0V to 5.5V)
72	RD0/AD0/PSP0	I/O	Multiplexed I/O & Peripheral Pin RD0/AD0/PSP0 (General)
73	IO73	I/O	General Purpose Digital I/O Pin IO73
74	RE6/AD14/P1B(2)	I/O	Multiplexed I/O & Peripheral Pin RE6/AD14/P1B(2) (General)
75	RE5/AD13/P1C(2)	I/O	Multiplexed I/O & Peripheral Pin RE5/AD13/P1C(2) (General)
76	RE4/AD12/P3B(2)	I/O	Multiplexed I/O & Peripheral Pin RE4/AD12/P3B(2) (General)
77	RE3/AD11/P3C(2)	I/O	Multiplexed I/O & Peripheral Pin RE3/AD11/P3C(2) (General)
78	RE2/AD10/CS#/P2B	I/O	Multiplexed I/O & Peripheral Pin RE2/AD10/CS#/P2B (General)
79	RH0/A16	I/O	Multiplexed I/O & Peripheral Pin RH0/A16 (General)
80	RH1/A17	I/O	Multiplexed I/O & Peripheral Pin RH1/A17 (General)

PIN 1 RH2/A18

I/O

Multiplexed I/O & Peripheral Pin RH2/A18 (General)

Design note: Signal terminal RH2/A18 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RH2/A18. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

PIC18F8527-I/PT (TQFP-80(12x12)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

PIC18F8527-I/PT (TQFP-80(12x12)) - 2. Standard Pinout (Top View)

True package pinout (80 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

PIC18F8527-I/PT (TQFP-80(12x12)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

PIC18F8527-I/PT (TQFP-80(12x12)) - 4. Package Dimensions (D×E×A)

TQFP-80(12x12) · 12.00×12.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

PIC18F8527-I/PT (TQFP-80(12x12)) - 5. Recommended Land Pattern

IPC-7351B Footprint (80 Pads)Expand ›

6. Application SchematicSCHEMATIC

PIC18F8527-I/PT (TQFP-80(12x12)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)

Showing 1–12 of 15 uncropped original figures for PIC18F8527

P2 · p02_fig011777×1640px

PIC18F8527-I/PT (TQFP-80(12x12)) — DS39646C-page ii © 2008 Microchip Technology Inc. | Trademarks | FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporate

DS39646C-page ii © 2008 Microchip Technology Inc. | Trademarks | FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporate

P2 · p02_fig02788×285px

PIC18F8527-I/PT (TQFP-80(12x12)) — DS39646C-page ii © 2008 Microchip Technology Inc.

P183 · p183_fig011777×345px

FIGURE 17-2: CAPTURE MODE OPERATION BLOCK DIAGRAM

P183 · p183_fig021427×504px

FIGURE 17-2: CAPTURE MODE OPERATION BLOCK DIAGRAM

P184 · p184_fig011611×642px

FIGURE 17-3: COMPARE MODE OPERATION BLOCK DIAGRAM

P211 · p211_fig011777×937px

FIGURE 19-2: SPI MASTER/SLAVE CONNECTION

P214 · p214_fig011777×1099px

FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx SCKx (CKP = 0 SCKx (CKP = 1 CKE = 0) Write to SSPxBUF

P214 · p214_fig021777×1119px

FIGURE 19-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx SCKx (CKP = 0 SCKx (CKP = 1 CKE = 1) Write to SSPxBUF

P214 · p214_fig01P214

Datasheet Page 214 (p214_fig01)

P421 · p421_fig02414×490px

Example

P421 · p421_fig03414×490px

80-Lead TQFP | XXXXXXXXXXXX XXXXXXXXXXXX | YYWWNNN

P421 · p421_fig04414×490px

Example | PIC18F8722-E /PT | 0810017 | 3 e

Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (PIC18F8527-I/PT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:PIC18F8527-I/PT (TQFP-80(12x12)) is a 80-pin standard electronic & interconnect component featuring a 12.00 × 12.00 × 1.20 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.0V to 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

2.0V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

32 kHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

12.00 × 12.00 × 1.20 mm (A1=0.10 mm)

Package family: TQFP (TQFP-80(12x12))

Pin Count & Lead PitchN / e

80 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

UART, SPI, I2C, ADC, PWM, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol80 auto-grouped pins

IPC-7351B Land Pattern80 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-80(12x12))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

12.00 × 12.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.20mm · e=0.50mm

Pad Size (W × L)Level B

0.30 × 1.25 mm

Pins / Total PadsTopology

80P / 80Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TQFP-80(12x12)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC18F8527-I/PT (TQFP-80(12x12))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC18F8527-I/PT (TQFP-80(12x12))?

Manufactured by MICROCHIP, the PIC18F8527-I/PT is housed in a TQFP-80(12x12) package with 80 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (RH2/A18: Multiplexed I/O & Peripheral Pin RH2/A18 (General)), 2 (RH3/A19: Multiplexed I/O & Peripheral Pin RH3/A19 (General)), 3 (RE1/AD9/WR#/P2C: Multiplexed I/O & Peripheral Pin RE1/AD9/WR#/P2C (General)), 4 (RE0/AD8/RD#/P2D: Multiplexed I/O & Peripheral Pin RE0/AD8/RD#/P2D (General)), 5 (RG0/ECCP3/P3A: Multiplexed I/O & Peripheral Pin RG0/ECCP3/P3A (General)), 6 (RG1/TX2/CK2: Multiplexed I/O & Peripheral Pin RG1/TX2/CK2 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC18F8527-I/PT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F8527-I/PT (TQFP-80(12x12)) has a nominal body envelope of 12.00 × 12.00 mm, pitch e = 0.50 mm, and 80 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F8527-I/PT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F8527-I/PT (MICROCHIP, TQFP-80(12x12)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (80 pins) & PIC18F8527 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	RH2/A18	Digital_IO	Signal terminal RH2/A18 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RH2/A18. Supported peripheral buses: General.
2	RH3/A19	Digital_IO	Signal terminal RH3/A19 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RH3/A19. Supported peripheral buses: General.
3	RE1/AD9/WR#/P2C	Digital_IO	Signal terminal RE1/AD9/WR#/P2C (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE1/AD9/WR#/P2C. Supported peripheral buses: General.
4	RE0/AD8/RD#/P2D	Digital_IO	Signal terminal RE0/AD8/RD#/P2D (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RE0/AD8/RD#/P2D. Supported peripheral buses: General.
5	RG0/ECCP3/P3A	Digital_IO	Signal terminal RG0/ECCP3/P3A (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RG0/ECCP3/P3A. Supported peripheral buses: General.
6	RG1/TX2/CK2	Digital_IO	Signal terminal RG1/TX2/CK2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RG1/TX2/CK2. Supported peripheral buses: General.
7	NC	No_Connect	No Connect (Leave Floating)
8	RG3/CCP4/P3D	Digital_IO	Signal terminal RG3/CCP4/P3D (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RG3/CCP4/P3D. Supported peripheral buses: General.
9	IO4	Digital_IO	GPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10	RG4/CCP5/P1D	Digital_IO	Signal terminal RG4/CCP5/P1D (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RG4/CCP5/P1D. Supported peripheral buses: General.
11	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
12	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
13	RF7/SS1@	RF_50Ohm	Signal terminal RF7/SS1@ (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RF7/SS1@. Supported peripheral buses: General.
14	RF6/AN11	RF_50Ohm	Signal terminal RF6/AN11 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RF6/AN11. Supported peripheral buses: General.
15	RF5/AN10/CVREF	RF_50Ohm	Signal terminal RF5/AN10/CVREF (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RF5/AN10/CVREF. Supported peripheral buses: General.
16	RF4/AN9	RF_50Ohm	Signal terminal RF4/AN9 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RF4/AN9. Supported peripheral buses: General.
17	RF3/AN8	RF_50Ohm	Signal terminal RF3/AN8 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RF3/AN8. Supported peripheral buses: General.
18	RF2/AN7/C1OUT	RF_50Ohm	Signal terminal RF2/AN7/C1OUT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RF2/AN7/C1OUT. Supported peripheral buses: General.
19	RH7/AN15/P1B(2)	Digital_IO	Signal terminal RH7/AN15/P1B(2) (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RH7/AN15/P1B(2). Supported peripheral buses: General.
20	RH6/AN14/P1C(2)	Digital_IO	Signal terminal RH6/AN14/P1C(2) (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RH6/AN14/P1C(2). Supported peripheral buses: General.
21	RH5/AN13/P3B(2)	Digital_IO	Signal terminal RH5/AN13/P3B(2) (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RH5/AN13/P3B(2). Supported peripheral buses: General.
22	RH4/AN12/P3C(2)	Digital_IO	Signal terminal RH4/AN12/P3C(2) (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RH4/AN12/P3C(2). Supported peripheral buses: General.
23	RF1/AN6/C2OUT	RF_50Ohm	Signal terminal RF1/AN6/C2OUT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RF1/AN6/C2OUT. Supported peripheral buses: General.
24	RF0/AN5	RF_50Ohm	Signal terminal RF0/AN5 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RF0/AN5. Supported peripheral buses: General.
25	AVDD	Power_In	Primary positive power supply input (AVDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
26	AVSS	GND	0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
27	RA3/AN3/VREF+	Analog	Signal terminal RA3/AN3/VREF+ (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
28	RA2/AN2/VREF-	Analog	Signal terminal RA2/AN2/VREF- (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF-. Supported peripheral buses: General.
29	RA1/AN1	Digital_IO	Signal terminal RA1/AN1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
30	RA0/AN0	Digital_IO	Signal terminal RA0/AN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
31	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
33	RA5/AN4/HLVDIN	Digital_IO	Signal terminal RA5/AN4/HLVDIN (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA5/AN4/HLVDIN. Supported peripheral buses: General.
34	RA4/T0CKI	Digital_IO	Signal terminal RA4/T0CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA4/T0CKI. Supported peripheral buses: General.
35	IO35	Digital_IO	General Purpose Digital I/O Pin IO35
36	RC0/T1OSO/T13CKI	Digital_IO	Signal terminal RC0/T1OSO/T13CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC0/T1OSO/T13CKI. Supported peripheral buses: General.
37	RC6/TX1/CK1	Digital_IO	Signal terminal RC6/TX1/CK1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC6/TX1/CK1. Supported peripheral buses: General.
38	RC7/RX1/DT1	Digital_IO	Signal terminal RC7/RX1/DT1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC7/RX1/DT1. Supported peripheral buses: General.
39	IO39	Digital_IO	General Purpose Digital I/O Pin IO39
40	IO40	Digital_IO	General Purpose Digital I/O Pin IO40
41	RJ6/LB#	Digital_IO	Signal terminal RJ6/LB# (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RJ6/LB#. Supported peripheral buses: General.
42	RJ7/UB#	Digital_IO	Signal terminal RJ7/UB# (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RJ7/UB#. Supported peripheral buses: General.
43	RC2/ECCP1/P1A	Digital_IO	Signal terminal RC2/ECCP1/P1A (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC2/ECCP1/P1A. Supported peripheral buses: General.
44	RC3/SCK1/SCL1	Digital_IO	Signal terminal RC3/SCK1/SCL1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC3/SCK1/SCL1. Supported peripheral buses: SPI, I2C.
45	RC4/SDI1/SDA1	Digital_IO	Signal terminal RC4/SDI1/SDA1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC4/SDI1/SDA1. Supported peripheral buses: I2C.
46	RC5/SDO1	Digital_IO	Signal terminal RC5/SDO1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC5/SDO1. Supported peripheral buses: General.
47	RB7/KBI3/PGD	Digital_IO	Signal terminal RB7/KBI3/PGD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB7/KBI3/PGD. Supported peripheral buses: General.
48	VDD	Power_In	Primary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
49	IO49	Digital_IO	General Purpose Digital I/O Pin IO49
50	IO50	Digital_IO	General Purpose Digital I/O Pin IO50
51	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
52	RB6/KBI2/PGC	Digital_IO	Signal terminal RB6/KBI2/PGC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB6/KBI2/PGC. Supported peripheral buses: General.
53	RB5/KBI1/PGM	Digital_IO	Signal terminal RB5/KBI1/PGM (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB5/KBI1/PGM. Supported peripheral buses: General.
54	RB4/KBI0	Digital_IO	Signal terminal RB4/KBI0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB4/KBI0. Supported peripheral buses: General.
55	IO55	Digital_IO	General Purpose Digital I/O Pin IO55
56	RB2/INT2	Digital_IO	Signal terminal RB2/INT2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB2/INT2. Supported peripheral buses: General.
57	RB1/INT1	Digital_IO	Signal terminal RB1/INT1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB1/INT1. Supported peripheral buses: General.
58	RB0/INT0	Digital_IO	Signal terminal RB0/INT0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB0/INT0. Supported peripheral buses: General.
59	RJ3/WRH#	Digital_IO	Signal terminal RJ3/WRH# (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RJ3/WRH#. Supported peripheral buses: General.
60	RJ2/WRL#	Digital_IO	Signal terminal RJ2/WRL# (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RJ2/WRL#. Supported peripheral buses: General.
61	RJ1/OE#	Digital_IO	Signal terminal RJ1/OE# (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RJ1/OE#. Supported peripheral buses: General.
62	RJ0/ALE	Digital_IO	Signal terminal RJ0/ALE (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RJ0/ALE. Supported peripheral buses: General.
63	RD7/AD7/PSP7/SS2#	Digital_IO	Signal terminal RD7/AD7/PSP7/SS2# (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD7/AD7/PSP7/SS2#. Supported peripheral buses: General.
64	RD6/AD6/PSP6/SCK2/SCL2	Digital_IO	Signal terminal RD6/AD6/PSP6/SCK2/SCL2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RD6/AD6/PSP6/SCK2/SCL2. Supported peripheral buses: SPI, I2C.

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