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CH347F (QFN-28(4X4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH347F

WCHID: C18221627QFN-28(4X4) · 29 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH347F (QFN-28(4X4))1XI2CTS13TXD14RXD15SCS06SCK7TDO8TDI9SCS110DTR1/TNOW111RI0/GPIO312TMS GPIO13RTS114SCK15ACT29PAD28UD+27UD-26SWDIO25GPIO624GPIO523SWDCLK22RXD021VCC20GND19TXD018RTS017CTS016MOSIGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.225.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
2CTS1I/OMultiplexed I/O & Peripheral Pin CTS1 (UART)
3TXD1I/OTXD1 (UART)
4RXD1I/ORXD1 (UART)
5SCS0I/OMultiplexed I/O & Peripheral Pin SCS0 (General)
6SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
7TDOI/OMultiplexed I/O & Peripheral Pin TDO (SWD/JTAG)
8TDII/OMultiplexed I/O & Peripheral Pin TDI (SWD/JTAG)
9SCS1I/OMultiplexed I/O & Peripheral Pin SCS1 (General)
10DTR1/TNOW1I/OMultiplexed I/O & Peripheral Pin DTR1/TNOW1 (UART)
11RI0/GPIO3I/OMultiplexed I/O & Peripheral Pin RI0/GPIO3 (UART)
12TMS GPIOI/OMultiplexed I/O & Peripheral Pin TMS GPIO (SWD/JTAG)
13RTS1I/OMultiplexed I/O & Peripheral Pin RTS1 (UART)
14SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
15ACTI/OMultiplexed I/O & Peripheral Pin ACT (USB, UART)
16MOSII/OMultiplexed I/O & Peripheral Pin MOSI (SPI)
17CTS0I/OMultiplexed I/O & Peripheral Pin CTS0 (UART)
18RTS0I/OMultiplexed I/O & Peripheral Pin RTS0 (UART)
19TXD0I/OTXD0 (UART)
20GNDGNDGround Reference Pin (GND)
21VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
22RXD0I/ORXD0 (UART)
23SWDCLKI/OMultiplexed I/O & Peripheral Pin SWDCLK (General)
24GPIO5I/OMultiplexed I/O & Peripheral Pin GPIO5 (General)
25GPIO6I/OMultiplexed I/O & Peripheral Pin GPIO6 (General)
26SWDIOI/OMultiplexed I/O & Peripheral Pin SWDIO (SWD/JTAG)
27UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
28UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
29PADI/OMultiplexed I/O & Peripheral Pin PAD (General)
PIN 1 XI
I/O
Multiplexed I/O & Peripheral Pin XI (RTC/CLK)
Design note: Signal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH347F (WCH · QFN-28(4X4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH347F (QFN-28(4X4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH347F (QFN-28(4X4)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH347F (QFN-28(4X4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH347F (QFN-28(4X4)) - 4. Package Dimensions (D×E×A)
QFN-28(4X4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH347F (QFN-28(4X4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH347F (QFN-28(4X4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)
Showing 1–11 of 11 uncropped original figures for CH347
P3 · p03_fig01EXACT PACKAGE
CH347F (QFN-28(4X4)) — 3、引脚排列
3、引脚排列
P3 · p03_fig02EXACT PACKAGE
CH347F (QFN-28(4X4)) — V1.4 3
V1.4 3
P8 · p08_fig01EXACT PACKAGE
CH347F (QFN-28(4X4)) — 5.2 工作模式说明
5.2 工作模式说明
P13 · p13_fig01EXACT PACKAGE
CH347F (QFN-28(4X4)) — 图8-1 USB 转双UART+I2C+SPI+JTAG 五合一的参考电路图
图8-1 USB 转双UART+I2C+SPI+JTAG 五合一的参考电路图
P1 · p01_fig011508×609px
CH347F (QFN-28(4X4)) — 图1-1 系统框图 2、特点 2.1 概述
图1-1 系统框图 2、特点 2.1 概述
P3 · p03_fig01P3
CH347F (QFN-28(4X4)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P4 · p04_fig011653×531px
CH347F (QFN-28(4X4)) — 引脚号 引脚名称 类型 引脚说明
引脚号 引脚名称 类型 引脚说明
P4 · p04_fig021699×466px
CH347F (QFN-28(4X4)) — 引脚号 引脚名称 类型 引脚说明
引脚号 引脚名称 类型 引脚说明
P4 · p04_fig031699×435px
CH347F (QFN-28(4X4)) — 26 SWDIO I/O (FT) SWD 接口的数据引脚
26 SWDIO I/O (FT) SWD 接口的数据引脚
P13 · p13_fig01P13
CH347F (QFN-28(4X4)) — Datasheet Page 13 (p13_fig01)
Datasheet Page 13 (p13_fig01)
P5 · p05_fig01All Packages in PDF
CH347F (QFN-28(4X4)) — V1.4 5
V1.4 5

Technical Specifications & Part Details (CH347F)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH347F (QFN-28(4X4)) is a 28-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, JTAG / SWD, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28(4X4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, JTAG / SWD, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28(4X4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28(4X4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH347F (QFN-28(4X4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH347F (QFN-28(4X4))?

Manufactured by WCH, the CH347F is housed in a QFN-28(4X4) package with 29 pins and a 0.50 mm lead pitch. Key pins include: 1 (XI: Multiplexed I/O & Peripheral Pin XI (RTC/CLK)), 2 (CTS1: Multiplexed I/O & Peripheral Pin CTS1 (UART)), 3 (TXD1: TXD1 (UART)), 4 (RXD1: RXD1 (UART)), 5 (SCS0: Multiplexed I/O & Peripheral Pin SCS0 (General)), 6 (SCK: Multiplexed I/O & Peripheral Pin SCK (SPI)).

What are the IPC-7351B PCB Footprint dimensions for CH347F?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH347F (QFN-28(4X4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH347F?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH347F (WCH, QFN-28(4X4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & CH347 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
2CTS1Digital_IOSignal terminal CTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1. Supported peripheral buses: UART.
3TXD1Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
4RXD1Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
5SCS0Digital_IOSignal terminal SCS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS0. Supported peripheral buses: General.
6SCKDigital_IOSignal terminal SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
7TDODigital_IOSignal terminal TDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TDO. Supported peripheral buses: SWD/JTAG.
8TDIDigital_IOSignal terminal TDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TDI. Supported peripheral buses: SWD/JTAG.
9SCS1Digital_IOSignal terminal SCS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS1. Supported peripheral buses: General.
10DTR1/TNOW1Digital_IOSignal terminal DTR1/TNOW1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR1/TNOW1. Supported peripheral buses: UART.
11RI0/GPIO3Digital_IOSignal terminal RI0/GPIO3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI0/GPIO3. Supported peripheral buses: UART.
12TMS GPIODigital_IOSignal terminal TMS GPIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TMS GPIO. Supported peripheral buses: SWD/JTAG.
13RTS1Digital_IOSignal terminal RTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS1. Supported peripheral buses: UART.
14SCKDigital_IOSignal terminal SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCK. Supported peripheral buses: SPI.
15ACTDigital_IOSignal terminal ACT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACT. Supported peripheral buses: USB, UART.
16MOSIDigital_IOSignal terminal MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MOSI. Supported peripheral buses: SPI.
17CTS0Digital_IOSignal terminal CTS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0. Supported peripheral buses: UART.
18RTS0Digital_IOSignal terminal RTS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS0. Supported peripheral buses: UART.
19TXD0Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
20GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
21VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
22RXD0Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
23SWDCLKDigital_IOSignal terminal SWDCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SWDCLK. Supported peripheral buses: General.
24GPIO5Digital_IOSignal terminal GPIO5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO5. Supported peripheral buses: General.
25GPIO6Digital_IOSignal terminal GPIO6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO6. Supported peripheral buses: General.
26SWDIODigital_IOSignal terminal SWDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SWDIO. Supported peripheral buses: SWD/JTAG.
27UD-Digital_IOSignal terminal UD- (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
28UD+Digital_IOSignal terminal UD+ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
29PADDigital_IOSignal terminal PAD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PAD. Supported peripheral buses: General.
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