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ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATMEGA64RFR2-ZU

MICROCHIPID: C1558308QFN-64-EP(9x9) · 65 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATMEGA64RFR2-ZU (QFN-64-EP(9x9))1DIEOV2[PF3:ADC3:DI3[PF4:ADC4:TC4[PF5:ADC5:TM5[PF6:ADC6:TD6[PF7:ADC7:TD7[AVSS_RFP]8[RFP]9[RFN]10[AVSS_RFN]11[TST]12[RSTN]13[RSTON]14[PG0:DIG3]15[PG1:DIG1]16[PG2:AMR]17[PG3:TOSC2]18[PG4:TOSC1]19[PG5:OC0B]20[DVSS:DSVSS]21[DVDD]22[DVDD]23[DEVDD]24[DVSS]25[PD0:SCL:INT26[PD1:SDA:INT27[PD2:RXD1:IN28[PD3:TXD1:IN29[PD4:ICP1]30[PD5:XCK1]31[PD6:T1]32[PD7:T0]33[CLKI]65[AVSS]64[PF1:ADC1]63[PF0:ADC0]62[AREF]61[AVSS]60[AVDD]59[EVDD]58[AVSS:ASVSS]57[XTAL1]56[XTAL2]55[DVSS]54[DEVDD]53[PE7:ICP3:IN52[PE6:T3:INT651[PE5:OC3C:IN50[PE4:OC3B:IN49[PE3:OC3A:AI48[PE2:XCK0:AI47[PE1:TXD0]46[PE0:RXD0:PC45[DVSS]44[DEVDD]43[PB7:OC0A:OC42[PB6:OC1B:PC41[PB5:OC1A:PC40[PB4:OC2A:PC39[PB3:MISO:PD38[PB2:MOSI:PD37[PB1:SCK:PCI36[PB0:SSN:PCI35[DVSS]34[DEVDD]Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.848.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465E=9.00mm · Pitch e=0.50mmD=9.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 9.00mm × 9.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (65/65)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DIEOVI/OMultiplexed I/O & Peripheral Pin DIEOV (General)
2[PF3:ADC3:DIG4]I/OMultiplexed I/O & Peripheral Pin [PF3:ADC3:DIG4] (ADC)
3[PF4:ADC4:TCK]I/OMultiplexed I/O & Peripheral Pin [PF4:ADC4:TCK] (ADC)
4[PF5:ADC5:TMS]I/OMultiplexed I/O & Peripheral Pin [PF5:ADC5:TMS] (ADC)
5[PF6:ADC6:TDO]I/OMultiplexed I/O & Peripheral Pin [PF6:ADC6:TDO] (ADC)
6[PF7:ADC7:TDI]I/OMultiplexed I/O & Peripheral Pin [PF7:ADC7:TDI] (ADC)
7[AVSS_RFP]GNDGround Reference Pin ([AVSS_RFP])
8[RFP]I/OMultiplexed I/O & Peripheral Pin [RFP] (General)
9[RFN]I/OMultiplexed I/O & Peripheral Pin [RFN] (General)
10[AVSS_RFN]GNDGround Reference Pin ([AVSS_RFN])
11[TST]I/OMultiplexed I/O & Peripheral Pin [TST] (General)
12[RSTN]I/OMultiplexed I/O & Peripheral Pin [RSTN] (General)
13[RSTON]I/OMultiplexed I/O & Peripheral Pin [RSTON] (General)
14[PG0:DIG3]I/OMultiplexed I/O & Peripheral Pin [PG0:DIG3] (General)
15[PG1:DIG1]I/OMultiplexed I/O & Peripheral Pin [PG1:DIG1] (General)
16[PG2:AMR]I/OMultiplexed I/O & Peripheral Pin [PG2:AMR] (General)
17[PG3:TOSC2]I/OMultiplexed I/O & Peripheral Pin [PG3:TOSC2] (General)
18[PG4:TOSC1]I/OMultiplexed I/O & Peripheral Pin [PG4:TOSC1] (General)
19[PG5:OC0B]I/OMultiplexed I/O & Peripheral Pin [PG5:OC0B] (PWM)
20[DVSS:DSVSS]GNDGround Reference Pin ([DVSS:DSVSS])
21[DVDD]PowerPower Supply Input ([DVDD] — 1.8V ~ 5.5V VCC)
22[DVDD]PowerPower Supply Input ([DVDD] — 1.8V ~ 5.5V VCC)
23[DEVDD]PowerPower Supply Input ([DEVDD] — 1.8V ~ 5.5V VCC)
24[DVSS]GNDGround Reference Pin ([DVSS])
25[PD0:SCL:INT0]I/OMultiplexed I/O & Peripheral Pin [PD0:SCL:INT0] (I2C)
26[PD1:SDA:INT1]I/OMultiplexed I/O & Peripheral Pin [PD1:SDA:INT1] (I2C)
27[PD2:RXD1:INT2]I/OMultiplexed I/O & Peripheral Pin [PD2:RXD1:INT2] (UART)
28[PD3:TXD1:INT3]I/OMultiplexed I/O & Peripheral Pin [PD3:TXD1:INT3] (UART)
29[PD4:ICP1]I/OMultiplexed I/O & Peripheral Pin [PD4:ICP1] (General)
30[PD5:XCK1]I/OMultiplexed I/O & Peripheral Pin [PD5:XCK1] (General)
31[PD6:T1]I/OMultiplexed I/O & Peripheral Pin [PD6:T1] (General)
32[PD7:T0]I/OMultiplexed I/O & Peripheral Pin [PD7:T0] (General)
33[CLKI]I/OMultiplexed I/O & Peripheral Pin [CLKI] (General)
34[DEVDD]PowerPower Supply Input ([DEVDD] — 1.8V ~ 5.5V VCC)
35[DVSS]GNDGround Reference Pin ([DVSS])
36[PB0:SSN:PCINT0]I/OMultiplexed I/O & Peripheral Pin [PB0:SSN:PCINT0] (General)
37[PB1:SCK:PCINT1]I/OMultiplexed I/O & Peripheral Pin [PB1:SCK:PCINT1] (SPI)
38[PB2:MOSI:PDI:PCINT2]I/OMultiplexed I/O & Peripheral Pin [PB2:MOSI:PDI:PCINT2] (SPI)
39[PB3:MISO:PDO:PCINT3]I/OMultiplexed I/O & Peripheral Pin [PB3:MISO:PDO:PCINT3] (SPI)
40[PB4:OC2A:PCINT4]I/OMultiplexed I/O & Peripheral Pin [PB4:OC2A:PCINT4] (PWM)
41[PB5:OC1A:PCINT5]I/OMultiplexed I/O & Peripheral Pin [PB5:OC1A:PCINT5] (PWM)
42[PB6:OC1B:PCINT6]I/OMultiplexed I/O & Peripheral Pin [PB6:OC1B:PCINT6] (PWM)
43[PB7:OC0A:OC1C:PCINT7]I/OMultiplexed I/O & Peripheral Pin [PB7:OC0A:OC1C:PCINT7] (PWM)
44[DEVDD]PowerPower Supply Input ([DEVDD] — 1.8V ~ 5.5V VCC)
45[DVSS]GNDGround Reference Pin ([DVSS])
46[PE0:RXD0:PCINT8]I/OMultiplexed I/O & Peripheral Pin [PE0:RXD0:PCINT8] (UART)
47[PE1:TXD0]I/OMultiplexed I/O & Peripheral Pin [PE1:TXD0] (UART)
48[PE2:XCK0:AIN0]I/OMultiplexed I/O & Peripheral Pin [PE2:XCK0:AIN0] (ADC)
49[PE3:OC3A:AIN1]I/OMultiplexed I/O & Peripheral Pin [PE3:OC3A:AIN1] (ADC, PWM)
50[PE4:OC3B:INT4]I/OMultiplexed I/O & Peripheral Pin [PE4:OC3B:INT4] (PWM)
51[PE5:OC3C:INT5]I/OMultiplexed I/O & Peripheral Pin [PE5:OC3C:INT5] (General)
52[PE6:T3:INT6]I/OMultiplexed I/O & Peripheral Pin [PE6:T3:INT6] (General)
53[PE7:ICP3:INT7:CLKO]I/OMultiplexed I/O & Peripheral Pin [PE7:ICP3:INT7:CLKO] (General)
54[DEVDD]PowerPower Supply Input ([DEVDD] — 1.8V ~ 5.5V VCC)
55[DVSS]GNDGround Reference Pin ([DVSS])
56[XTAL2]I/OMultiplexed I/O & Peripheral Pin [XTAL2] (RTC/CLK)
57[XTAL1]I/OMultiplexed I/O & Peripheral Pin [XTAL1] (RTC/CLK)
58[AVSS:ASVSS]GNDGround Reference Pin ([AVSS:ASVSS])
59[EVDD]PowerPower Supply Input ([EVDD] — 1.8V ~ 5.5V VCC)
60[AVDD]PowerPower Supply Input ([AVDD] — 1.8V ~ 5.5V VCC)
61[AVSS]GNDGround Reference Pin ([AVSS])
62[AREF]I/OMultiplexed I/O & Peripheral Pin [AREF] (ADC)
63[PF0:ADC0]I/OMultiplexed I/O & Peripheral Pin [PF0:ADC0] (ADC)
64[PF1:ADC1]I/OMultiplexed I/O & Peripheral Pin [PF1:ADC1] (ADC)
65[AVSS]GNDExposed Thermal & Ground Pad ([AVSS])
PIN 1 DIEOV
I/O
Multiplexed I/O & Peripheral Pin DIEOV (General)
Design note: Signal terminal DIEOV (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: DIEOV. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATMEGA64RFR2-ZU (MICROCHIP · QFN-64-EP(9x9))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) - 2. Standard Pinout (Top View)
True package pinout (65 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) - 4. Package Dimensions (D×E×A)
QFN-64-EP(9x9) · 9.00×9.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) - 5. Recommended Land Pattern
IPC-7351B Footprint (65 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for ATMEGA64RFR2
P1 · p01_fig012138×2590px
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) — 1
1
P2 · p02_fig011642×1288px
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) — Figure 1-1. Pinout ATmega256/128/64RFR2
Figure 1-1. Pinout ATmega256/128/64RFR2
P2 · p02_fig01P2
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P87 · p87_fig011102×855px
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) — Figure 9-26. Simplified XOSC Schematic with External Components
Figure 9-26. Simplified XOSC Schematic with External Components
P540 · p540_fig011282×1274px
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) — Figure 32-1. Basic Application schematic (64-pin package)
Figure 32-1. Basic Application schematic (64-pin package)
P540 · p540_fig01P540
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) — Datasheet Page 540 (p540_fig01)
Datasheet Page 540 (p540_fig01)
P597 · p597_fig012056×2486px
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) — 597
597
P597 · p597_fig01P597
ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) — Datasheet Page 597 (p597_fig01)
Datasheet Page 597 (p597_fig01)

Technical Specifications & Part Details (ATMEGA64RFR2-ZU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) is a 64-pin embedded microcontroller unit (mcu) featuring a 9.00 × 9.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V supply operation across -40°C to 125°C with integrated UART, SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
65 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
9.00 × 9.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (QFN-64-EP(9x9))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol65 auto-grouped pins
OK
IPC-7351B Land Pattern65 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.65×4.75mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-64-EP(9x9))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 9.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
65P / 65Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-64-EP(9x9)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATMEGA64RFR2-ZU (QFN-64-EP(9x9))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATMEGA64RFR2-ZU (QFN-64-EP(9x9))?

Manufactured by MICROCHIP, the ATMEGA64RFR2-ZU is housed in a QFN-64-EP(9x9) package with 65 pins and a 0.50 mm lead pitch. Key pins include: 1 (DIEOV: Multiplexed I/O & Peripheral Pin DIEOV (General)), 2 ([PF3:ADC3:DIG4]: Multiplexed I/O & Peripheral Pin [PF3:ADC3:DIG4] (ADC)), 3 ([PF4:ADC4:TCK]: Multiplexed I/O & Peripheral Pin [PF4:ADC4:TCK] (ADC)), 4 ([PF5:ADC5:TMS]: Multiplexed I/O & Peripheral Pin [PF5:ADC5:TMS] (ADC)), 5 ([PF6:ADC6:TDO]: Multiplexed I/O & Peripheral Pin [PF6:ADC6:TDO] (ADC)), 6 ([PF7:ADC7:TDI]: Multiplexed I/O & Peripheral Pin [PF7:ADC7:TDI] (ADC)).

What are the IPC-7351B PCB Footprint dimensions for ATMEGA64RFR2-ZU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATMEGA64RFR2-ZU (QFN-64-EP(9x9)) has a nominal body envelope of 9.00 × 9.00 mm, pitch e = 0.50 mm, and 65 copper pads plus a central exposed thermal pad (EPAD) of 5.65 × 4.75 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATMEGA64RFR2-ZU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATMEGA64RFR2-ZU (MICROCHIP, QFN-64-EP(9x9)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (65 pins) & ATMEGA64RFR2 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DIEOVDigital_IOSignal terminal DIEOV (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: DIEOV. Supported peripheral buses: General.
2[PF3:ADC3:DIG4]AnalogSignal terminal [PF3:ADC3:DIG4] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PF3:ADC3:DIG4]. Supported peripheral buses: ADC.
3[PF4:ADC4:TCK]AnalogSignal terminal [PF4:ADC4:TCK] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PF4:ADC4:TCK]. Supported peripheral buses: ADC.
4[PF5:ADC5:TMS]AnalogSignal terminal [PF5:ADC5:TMS] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PF5:ADC5:TMS]. Supported peripheral buses: ADC.
5[PF6:ADC6:TDO]AnalogSignal terminal [PF6:ADC6:TDO] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PF6:ADC6:TDO]. Supported peripheral buses: ADC.
6[PF7:ADC7:TDI]AnalogSignal terminal [PF7:ADC7:TDI] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PF7:ADC7:TDI]. Supported peripheral buses: ADC.
7[AVSS_RFP]GND0V electrical ground return terminal ([AVSS_RFP]) for internal core logic, I/O drivers, and analog sub-blocks.
8[RFP]RF_50OhmSignal terminal [RFP] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [RFP]. Supported peripheral buses: General.
9[RFN]RF_50OhmSignal terminal [RFN] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [RFN]. Supported peripheral buses: General.
10[AVSS_RFN]GND0V electrical ground return terminal ([AVSS_RFN]) for internal core logic, I/O drivers, and analog sub-blocks.
11[TST]Digital_IOSignal terminal [TST] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [TST]. Supported peripheral buses: General.
12[RSTN]Digital_IOSignal terminal [RSTN] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [RSTN]. Supported peripheral buses: General.
13[RSTON]Digital_IOSignal terminal [RSTON] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [RSTON]. Supported peripheral buses: General.
14[PG0:DIG3]Digital_IOSignal terminal [PG0:DIG3] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PG0:DIG3]. Supported peripheral buses: General.
15[PG1:DIG1]Digital_IOSignal terminal [PG1:DIG1] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PG1:DIG1]. Supported peripheral buses: General.
16[PG2:AMR]Digital_IOSignal terminal [PG2:AMR] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PG2:AMR]. Supported peripheral buses: General.
17[PG3:TOSC2]Digital_IOSignal terminal [PG3:TOSC2] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PG3:TOSC2]. Supported peripheral buses: General.
18[PG4:TOSC1]Digital_IOSignal terminal [PG4:TOSC1] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PG4:TOSC1]. Supported peripheral buses: General.
19[PG5:OC0B]Digital_IOSignal terminal [PG5:OC0B] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PG5:OC0B]. Supported peripheral buses: PWM.
20[DVSS:DSVSS]GND0V electrical ground return terminal ([DVSS:DSVSS]) for internal core logic, I/O drivers, and analog sub-blocks.
21[DVDD]Power_InPrimary positive power supply input ([DVDD]) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
22[DVDD]Power_InPrimary positive power supply input ([DVDD]) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
23[DEVDD]Power_InPrimary positive power supply input ([DEVDD]) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
24[DVSS]GND0V electrical ground return terminal ([DVSS]) for internal core logic, I/O drivers, and analog sub-blocks.
25[PD0:SCL:INT0]Digital_IOSignal terminal [PD0:SCL:INT0] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PD0:SCL:INT0]. Supported peripheral buses: I2C.
26[PD1:SDA:INT1]Digital_IOSignal terminal [PD1:SDA:INT1] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PD1:SDA:INT1]. Supported peripheral buses: I2C.
27[PD2:RXD1:INT2]Digital_IOSignal terminal [PD2:RXD1:INT2] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PD2:RXD1:INT2]. Supported peripheral buses: UART.
28[PD3:TXD1:INT3]Digital_IOSignal terminal [PD3:TXD1:INT3] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PD3:TXD1:INT3]. Supported peripheral buses: UART.
29[PD4:ICP1]Digital_IOSignal terminal [PD4:ICP1] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PD4:ICP1]. Supported peripheral buses: General.
30[PD5:XCK1]Digital_IOSignal terminal [PD5:XCK1] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PD5:XCK1]. Supported peripheral buses: General.
31[PD6:T1]Digital_IOSignal terminal [PD6:T1] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PD6:T1]. Supported peripheral buses: General.
32[PD7:T0]Digital_IOSignal terminal [PD7:T0] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PD7:T0]. Supported peripheral buses: General.
33[CLKI]Digital_IOSignal terminal [CLKI] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [CLKI]. Supported peripheral buses: General.
34[DEVDD]Power_InPrimary positive power supply input ([DEVDD]) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
35[DVSS]GND0V electrical ground return terminal ([DVSS]) for internal core logic, I/O drivers, and analog sub-blocks.
36[PB0:SSN:PCINT0]Digital_IOSignal terminal [PB0:SSN:PCINT0] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PB0:SSN:PCINT0]. Supported peripheral buses: General.
37[PB1:SCK:PCINT1]Digital_IOSignal terminal [PB1:SCK:PCINT1] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PB1:SCK:PCINT1]. Supported peripheral buses: SPI.
38[PB2:MOSI:PDI:PCINT2]Digital_IOSignal terminal [PB2:MOSI:PDI:PCINT2] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PB2:MOSI:PDI:PCINT2]. Supported peripheral buses: SPI.
39[PB3:MISO:PDO:PCINT3]Digital_IOSignal terminal [PB3:MISO:PDO:PCINT3] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PB3:MISO:PDO:PCINT3]. Supported peripheral buses: SPI.
40[PB4:OC2A:PCINT4]Digital_IOSignal terminal [PB4:OC2A:PCINT4] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PB4:OC2A:PCINT4]. Supported peripheral buses: PWM.
41[PB5:OC1A:PCINT5]Digital_IOSignal terminal [PB5:OC1A:PCINT5] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PB5:OC1A:PCINT5]. Supported peripheral buses: PWM.
42[PB6:OC1B:PCINT6]Digital_IOSignal terminal [PB6:OC1B:PCINT6] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PB6:OC1B:PCINT6]. Supported peripheral buses: PWM.
43[PB7:OC0A:OC1C:PCINT7]Digital_IOSignal terminal [PB7:OC0A:OC1C:PCINT7] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PB7:OC0A:OC1C:PCINT7]. Supported peripheral buses: PWM.
44[DEVDD]Power_InPrimary positive power supply input ([DEVDD]) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
45[DVSS]GND0V electrical ground return terminal ([DVSS]) for internal core logic, I/O drivers, and analog sub-blocks.
46[PE0:RXD0:PCINT8]Digital_IOSignal terminal [PE0:RXD0:PCINT8] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PE0:RXD0:PCINT8]. Supported peripheral buses: UART.
47[PE1:TXD0]Digital_IOSignal terminal [PE1:TXD0] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PE1:TXD0]. Supported peripheral buses: UART.
48[PE2:XCK0:AIN0]AnalogSignal terminal [PE2:XCK0:AIN0] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PE2:XCK0:AIN0]. Supported peripheral buses: ADC.
49[PE3:OC3A:AIN1]AnalogSignal terminal [PE3:OC3A:AIN1] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PE3:OC3A:AIN1]. Supported peripheral buses: ADC, PWM.
50[PE4:OC3B:INT4]Digital_IOSignal terminal [PE4:OC3B:INT4] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PE4:OC3B:INT4]. Supported peripheral buses: PWM.
51[PE5:OC3C:INT5]Digital_IOSignal terminal [PE5:OC3C:INT5] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PE5:OC3C:INT5]. Supported peripheral buses: General.
52[PE6:T3:INT6]Digital_IOSignal terminal [PE6:T3:INT6] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PE6:T3:INT6]. Supported peripheral buses: General.
53[PE7:ICP3:INT7:CLKO]Digital_IOSignal terminal [PE7:ICP3:INT7:CLKO] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PE7:ICP3:INT7:CLKO]. Supported peripheral buses: General.
54[DEVDD]Power_InPrimary positive power supply input ([DEVDD]) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
55[DVSS]GND0V electrical ground return terminal ([DVSS]) for internal core logic, I/O drivers, and analog sub-blocks.
56[XTAL2]Digital_IOSignal terminal [XTAL2] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [XTAL2]. Supported peripheral buses: RTC/CLK.
57[XTAL1]Digital_IOSignal terminal [XTAL1] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [XTAL1]. Supported peripheral buses: RTC/CLK.
58[AVSS:ASVSS]GND0V electrical ground return terminal ([AVSS:ASVSS]) for internal core logic, I/O drivers, and analog sub-blocks.
59[EVDD]Power_InPrimary positive power supply input ([EVDD]) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
60[AVDD]Power_InPrimary positive power supply input ([AVDD]) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
61[AVSS]GND0V electrical ground return terminal ([AVSS]) for internal core logic, I/O drivers, and analog sub-blocks.
62[AREF]Digital_IOSignal terminal [AREF] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [AREF]. Supported peripheral buses: ADC.
63[PF0:ADC0]AnalogSignal terminal [PF0:ADC0] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PF0:ADC0]. Supported peripheral buses: ADC.
64[PF1:ADC1]AnalogSignal terminal [PF1:ADC1] (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: [PF1:ADC1]. Supported peripheral buses: ADC.
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