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SG1843J-DESC (SOIC-14) — Symbol, Footprint IPC-7351B & 3D STEP Model

SG1843J-DESC

MICROCHIPID: C1530294SOIC-14 · 14 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · SG1843J-DESC (SOIC-14)1COM2NC3VFB4NC5ISENSE6NC7RT/CT14VREF13NC12VCC11VC10OUTPUT9GND8PWR GNDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.815.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
1234567891011121314E=3.90mm · Pitch e=1.27mmD=8.65mm-5-4-3-2-10123456543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 3.90mm × 8.65mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (14/14)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1COMI/OMultiplexed I/O & Peripheral Pin COM (General)
2NCI/OMultiplexed I/O & Peripheral Pin NC (General)
3VFBI/OMultiplexed I/O & Peripheral Pin VFB (General)
4NCI/OMultiplexed I/O & Peripheral Pin NC (General)
5ISENSEI/OMultiplexed I/O & Peripheral Pin ISENSE (General)
6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
7RT/CTI/OMultiplexed I/O & Peripheral Pin RT/CT (General)
8PWR GNDGNDGround Reference Pin (PWR GND)
9GNDGNDGround Reference Pin (GND)
10OUTPUTI/OMultiplexed I/O & Peripheral Pin OUTPUT (General)
11VCI/OMultiplexed I/O & Peripheral Pin VC (General)
12VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
13NCI/OMultiplexed I/O & Peripheral Pin NC (General)
14VREFAnalogMultiplexed I/O & Peripheral Pin VREF (General)
PIN 1 COM
I/O
Multiplexed I/O & Peripheral Pin COM (General)
Design note: Signal terminal COM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: COM. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: SG1843J-DESC (MICROCHIP · SOIC-14)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
SG1843J-DESC (SOIC-14) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
SG1843J-DESC (SOIC-14) - 2. Standard Pinout (Top View)
True package pinout (14 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
SG1843J-DESC (SOIC-14) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SG1843J-DESC (SOIC-14) - 4. Package Dimensions (D×E×A)
SOIC-14 · 3.90×8.65mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
SG1843J-DESC (SOIC-14) - 5. Recommended Land Pattern
IPC-7351B Footprint (14 Pads)Expand ›
6. Application SchematicSCHEMATIC
SG1843J-DESC (SOIC-14) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for SG1843
P13 · p13_fig01EXACT PACKAGE
SG1843J-DESC (SOIC-14) — Figure 17 · Current Sense Spike Suppression
Figure 17 · Current Sense Spike Suppression
P22 · p22_fig01EXACT PACKAGE
SG1843J-DESC (SOIC-14) — Figure 5 · N 14-Pin PDIP Package Dimensions
Figure 5 · N 14-Pin PDIP Package Dimensions
P22 · p22_fig02EXACT PACKAGE
SG1843J-DESC (SOIC-14) — Figure 5 · N 14-Pin PDIP Package Dimensions
Figure 5 · N 14-Pin PDIP Package Dimensions
P1 · p01_fig011865×1211px
SG1843J-DESC (SOIC-14) — Current Mode PWM Controller
Current Mode PWM Controller
P1 · p01_fig021049×808px
SG1843J-DESC (SOIC-14) — Figure 1 · Product Highlight
Figure 1 · Product Highlight
P11 · p11_fig01909×849px
SG1843J-DESC (SOIC-14) — Figure 15 · Oscillator Timing Circuit
Figure 15 · Oscillator Timing Circuit
P13 · p13_fig02713×877px
SG1843J-DESC (SOIC-14) — Figure 18 · MOSFET Parasitic Oscillations
Figure 18 · MOSFET Parasitic Oscillations
P13 · p13_fig01P13
SG1843J-DESC (SOIC-14) — Datasheet Page 13 (p13_fig01)
Datasheet Page 13 (p13_fig01)
P15 · p15_fig011117×808px
SG1843J-DESC (SOIC-14) — Figure 21 · Adjustable Buffered Reduction of Clamp Level with Softstart Where, VCS=1.67 ൬ R1 R1+R2൰ and VC.S.MAX = 1V (Typ.)
Figure 21 · Adjustable Buffered Reduction of Clamp Level with Softstart Where, VCS=1.67 ൬ R1 R1+R2൰ and VC.S.MAX = 1V (Typ.)
P15 · p15_fig021022×891px
SG1843J-DESC (SOIC-14) — Figure 22 · External Duty Cycle Clamp and Multi-Unit Synchronization
Figure 22 · External Duty Cycle Clamp and Multi-Unit Synchronization
P21 · p21_fig011804×782px
SG1843J-DESC (SOIC-14) — Package Outline Dimensions
Package Outline Dimensions
P22 · p22_fig02P22
SG1843J-DESC (SOIC-14) — Datasheet Page 22 (p22_fig02)
Datasheet Page 22 (p22_fig02)
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (SG1843J-DESC)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:SG1843J-DESC (SOIC-14) is a 14-pin standard electronic & interconnect component featuring a 8.65 × 3.90 × 1.75 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -55°C to 125°C with integrated PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-55°C to 125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
500kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.65 × 3.90 × 1.75 mm (A1=0.17 mm)
Package family: SOIC (SOIC-14)
Pin Count & Lead PitchN / e
14 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol14 auto-grouped pins
OK
IPC-7351B Land Pattern14 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-14)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.65 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.75mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
14P / 14Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOIC-14
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — SG1843J-DESC (SOIC-14)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of SG1843J-DESC (SOIC-14)?

Manufactured by MICROCHIP, the SG1843J-DESC is housed in a SOIC-14 package with 14 pins and a 1.27 mm lead pitch. Key pins include: 1 (COM: Multiplexed I/O & Peripheral Pin COM (General)), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (VFB: Multiplexed I/O & Peripheral Pin VFB (General)), 4 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 5 (ISENSE: Multiplexed I/O & Peripheral Pin ISENSE (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for SG1843J-DESC?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SG1843J-DESC (SOIC-14) has a nominal body envelope of 3.90 × 8.65 mm, pitch e = 1.27 mm, and 14 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SG1843J-DESC?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SG1843J-DESC (MICROCHIP, SOIC-14) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (14 pins) & SG1843 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1COMDigital_IOSignal terminal COM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: COM. Supported peripheral buses: General.
2NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
3VFBDigital_IOSignal terminal VFB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VFB. Supported peripheral buses: General.
4NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
5ISENSEDigital_IOSignal terminal ISENSE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ISENSE. Supported peripheral buses: General.
6NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7RT/CTDigital_IOSignal terminal RT/CT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RT/CT. Supported peripheral buses: General.
8PWR GNDGND0V electrical ground return terminal (PWR GND) for internal core logic, I/O drivers, and analog sub-blocks.
9GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
10OUTPUTDigital_IOSignal terminal OUTPUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OUTPUT. Supported peripheral buses: General.
11VCDigital_IOSignal terminal VC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VC. Supported peripheral buses: General.
12VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
13NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14VREFAnalogSignal terminal VREF (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VREF. Supported peripheral buses: General.
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