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AT42QT2120-XU (TSSOP-20) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT42QT2120-XU

MICROCHIPID: C1522278TSSOP-20 · 20 Pins · Pitch 0.65mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT42QT2120-XU (TSSOP-20)1KEY8/ GPO62KEY7/ GPO53KEY6/ GPO44KEY5/ GPO35KEY4/ GPO26KEY3/ GPO17KEY2/ GPO08KEY19KEY010VSS20KEY9/ GPO719KEY10/ GPO818KEY11/ GPO917CHANGE16SCL15N/C14RESET13SDA12MODE11VDDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617181920E=4.40mm · Pitch e=0.65mmD=6.50mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 4.40mm × 6.50mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1KEY8/ GPO6I/OMultiplexed I/O & Peripheral Pin KEY8/ GPO6 (General)
2KEY7/ GPO5I/OMultiplexed I/O & Peripheral Pin KEY7/ GPO5 (General)
3KEY6/ GPO4I/OMultiplexed I/O & Peripheral Pin KEY6/ GPO4 (General)
4KEY5/ GPO3I/OMultiplexed I/O & Peripheral Pin KEY5/ GPO3 (General)
5KEY4/ GPO2I/OMultiplexed I/O & Peripheral Pin KEY4/ GPO2 (General)
6KEY3/ GPO1I/OMultiplexed I/O & Peripheral Pin KEY3/ GPO1 (General)
7KEY2/ GPO0I/OMultiplexed I/O & Peripheral Pin KEY2/ GPO0 (General)
8KEY1I/OMultiplexed I/O & Peripheral Pin KEY1 (General)
9KEY0I/OMultiplexed I/O & Peripheral Pin KEY0 (General)
10VSSGNDGround Reference Pin (VSS)
11VDDPowerPower Supply Input (VDD — 1.8 V to 5.5 V)
12MODEI/OMultiplexed I/O & Peripheral Pin MODE (General)
13SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
14RESETISystem Enable & Hardware Reset (RESET)
15N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
16SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
17CHANGEI/OMultiplexed I/O & Peripheral Pin CHANGE (General)
18KEY11/ GPO9I/OMultiplexed I/O & Peripheral Pin KEY11/ GPO9 (General)
19KEY10/ GPO8I/OMultiplexed I/O & Peripheral Pin KEY10/ GPO8 (General)
20KEY9/ GPO7I/OMultiplexed I/O & Peripheral Pin KEY9/ GPO7 (General)
PIN 1 KEY8/ GPO6
I/O
Multiplexed I/O & Peripheral Pin KEY8/ GPO6 (General)
Design note: Comms mode: Key 8 / General -purpose output Standalone mode: push -pull output for key 3
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: AT42QT2120-XU (MICROCHIP · TSSOP-20)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
AT42QT2120-XU (TSSOP-20) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT42QT2120-XU (TSSOP-20) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT42QT2120-XU (TSSOP-20) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT42QT2120-XU (TSSOP-20) - 4. Package Dimensions (D×E×A)
TSSOP-20 · 4.40×6.50mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT42QT2120-XU (TSSOP-20) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT42QT2120-XU (TSSOP-20) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for AT42QT2120
P2 · p02_fig01EXACT PACKAGE
AT42QT2120-XU (TSSOP-20) — OUT3
OUT3
P2 · p02_fig02EXACT PACKAGE
AT42QT2120-XU (TSSOP-20) — VDD
VDD
P34 · p34_fig01EXACT PACKAGE
AT42QT2120-XU (TSSOP-20) — 34 | 9634E-AT42-06/12 AT42QT2120 | 6.6 Mechanical Dimensions | 6.6.1 AT42QT2120-SU - 20-pin SOIC
34 | 9634E-AT42-06/12 AT42QT2120 | 6.6 Mechanical Dimensions | 6.6.1 AT42QT2120-SU - 20-pin SOIC
P35 · p35_fig01EXACT PACKAGE
AT42QT2120-XU (TSSOP-20) — 35 | 9634E-AT42-06/12 | AT42QT2120 | 6.6.2 AT42QT2120-XU - 20-pin TSSOP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 20X, (Formerly 20T), 20-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSS
35 | 9634E-AT42-06/12 | AT42QT2120 | 6.6.2 AT42QT2120-XU - 20-pin TSSOP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 20X, (Formerly 20T), 20-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSS
P36 · p36_fig01EXACT PACKAGE
AT42QT2120-XU (TSSOP-20) — 36 | 9634E-AT42-06/12 AT42QT2120 | 6.6.3 AT42QT2120-MMH - 20-pin VQFN | TITLE DRAWING NO. GPC REV. | Package Drawing Contact: packagedrawings@atmel.com 20M2 ZFC B 20M2, 20-pad, 3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm, 1.55 x 1.55 mm Expose
36 | 9634E-AT42-06/12 AT42QT2120 | 6.6.3 AT42QT2120-MMH - 20-pin VQFN | TITLE DRAWING NO. GPC REV. | Package Drawing Contact: packagedrawings@atmel.com 20M2 ZFC B 20M2, 20-pad, 3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm, 1.55 x 1.55 mm Expose
P1 · p01_fig01652×450px
AT42QT2120-XU (TSSOP-20) — QTouch 12-channel Touch Sensor IC
QTouch 12-channel Touch Sensor IC
P2 · p02_fig01P2
AT42QT2120-XU (TSSOP-20) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P35 · p35_fig01P35
AT42QT2120-XU (TSSOP-20) — Datasheet Page 35 (p35_fig01)
Datasheet Page 35 (p35_fig01)

Technical Specifications & Part Details (AT42QT2120-XU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT42QT2120-XU (TSSOP-20) is a 20-pin standard electronic & interconnect component featuring a 6.50 × 4.40 × 1.20 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8 V to 5.5 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8 V to 5.5 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
400 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.50 × 4.40 × 1.20 mm (A1=0.10 mm)
Package family: TSSOP (TSSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TSSOP-20)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.50 × 4.40 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.45 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TSSOP-20
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT42QT2120-XU (TSSOP-20)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT42QT2120-XU (TSSOP-20)?

Manufactured by MICROCHIP, the AT42QT2120-XU is housed in a TSSOP-20 package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 1.8 V to 5.5 V. Key pins include: 1 (KEY8/ GPO6: Multiplexed I/O & Peripheral Pin KEY8/ GPO6 (General)), 2 (KEY7/ GPO5: Multiplexed I/O & Peripheral Pin KEY7/ GPO5 (General)), 3 (KEY6/ GPO4: Multiplexed I/O & Peripheral Pin KEY6/ GPO4 (General)), 4 (KEY5/ GPO3: Multiplexed I/O & Peripheral Pin KEY5/ GPO3 (General)), 5 (KEY4/ GPO2: Multiplexed I/O & Peripheral Pin KEY4/ GPO2 (General)), 6 (KEY3/ GPO1: Multiplexed I/O & Peripheral Pin KEY3/ GPO1 (General)).

What are the IPC-7351B PCB Footprint dimensions for AT42QT2120-XU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT42QT2120-XU (TSSOP-20) has a nominal body envelope of 4.40 × 6.50 mm, pitch e = 0.65 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT42QT2120-XU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT42QT2120-XU (MICROCHIP, TSSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & AT42QT2120 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1KEY8/ GPO6Digital_IOSignal terminal KEY8/ GPO6 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY8/ GPO6. Supported peripheral buses: General.
2KEY7/ GPO5Digital_IOSignal terminal KEY7/ GPO5 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY7/ GPO5. Supported peripheral buses: General.
3KEY6/ GPO4Digital_IOSignal terminal KEY6/ GPO4 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY6/ GPO4. Supported peripheral buses: General.
4KEY5/ GPO3Digital_IOSignal terminal KEY5/ GPO3 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY5/ GPO3. Supported peripheral buses: General.
5KEY4/ GPO2Digital_IOSignal terminal KEY4/ GPO2 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY4/ GPO2. Supported peripheral buses: General.
6KEY3/ GPO1Digital_IOSignal terminal KEY3/ GPO1 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY3/ GPO1. Supported peripheral buses: General.
7KEY2/ GPO0Digital_IOSignal terminal KEY2/ GPO0 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY2/ GPO0. Supported peripheral buses: General.
8KEY1Digital_IOSignal terminal KEY1 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY1. Supported peripheral buses: General.
9KEY0Digital_IOSignal terminal KEY0 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY0. Supported peripheral buses: General.
10VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
11VDDPower_InPrimary positive power supply input (VDD) operating in the 1.8 V to 5.5 V domain (Max rating: 5.5V).
12MODEDigital_IOSignal terminal MODE (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: MODE. Supported peripheral buses: General.
13SDADigital_IOSignal terminal SDA (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
14RESETDigital_IOActive-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
15N/CDigital_IOSignal terminal N/C (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: N/C. Supported peripheral buses: General.
16SCLDigital_IOSignal terminal SCL (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
17CHANGEDigital_IOSignal terminal CHANGE (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: CHANGE. Supported peripheral buses: General.
18KEY11/ GPO9Digital_IOSignal terminal KEY11/ GPO9 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY11/ GPO9. Supported peripheral buses: General.
19KEY10/ GPO8Digital_IOSignal terminal KEY10/ GPO8 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY10/ GPO8. Supported peripheral buses: General.
20KEY9/ GPO7Digital_IOSignal terminal KEY9/ GPO7 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: KEY9/ GPO7. Supported peripheral buses: General.
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