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AT42QT1481-AU (TQFP-44(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT42QT1481-AU

MICROCHIPID: C1522269TQFP-44(10x10) · 44 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT42QT1481-AU (TQFP-44(10x10))1MOSI2MISO3SCK4RST5VDD6VSS7XT28XT19RX10TX11WS12SMP13Y3A14Y2A15Y1A16Y0A17VDD18VSS19X020X121X222X344SS43S SYNC/_ DBG42VREF41DRDY40STATUS/ DBG_39VSS38VDD37Y5B36Y5A35Y4B34Y4A33Y3B32Y2B31Y1B30Y0B29VDD28VSS27VDD26X725X624X523X4Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.833.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344E=10.00mm · Pitch e=0.80mmD=10.00mm-10-8-6-4-202468101086420-2-4-6-8-10mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (44/44)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1MOSII/OMultiplexed I/O & Peripheral Pin MOSI (SPI)
2MISOI/OMultiplexed I/O & Peripheral Pin MISO (SPI)
3SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
4RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
5VDDPowerPower Supply Input (VDD — 4.75 V to 5.25 V)
6VSSGNDGround Reference Pin (VSS)
7XT2I/OMultiplexed I/O & Peripheral Pin XT2 (General)
8XT1I/OMultiplexed I/O & Peripheral Pin XT1 (General)
9RXI/OMultiplexed I/O & Peripheral Pin RX (UART)
10TXI/OMultiplexed I/O & Peripheral Pin TX (UART)
11WSI/OMultiplexed I/O & Peripheral Pin WS (General)
12SMPI/OMultiplexed I/O & Peripheral Pin SMP (General)
13Y3AI/OMultiplexed I/O & Peripheral Pin Y3A (General)
14Y2AI/OMultiplexed I/O & Peripheral Pin Y2A (General)
15Y1AI/OMultiplexed I/O & Peripheral Pin Y1A (General)
16Y0AI/OMultiplexed I/O & Peripheral Pin Y0A (General)
17VDDPowerPower Supply Input (VDD — 4.75 V to 5.25 V)
18VSSGNDGround Reference Pin (VSS)
19X0I/OMultiplexed I/O & Peripheral Pin X0 (General)
20X1I/OMultiplexed I/O & Peripheral Pin X1 (General)
21X2I/OMultiplexed I/O & Peripheral Pin X2 (General)
22X3I/OMultiplexed I/O & Peripheral Pin X3 (General)
23X4I/OMultiplexed I/O & Peripheral Pin X4 (General)
24X5I/OMultiplexed I/O & Peripheral Pin X5 (General)
25X6I/OMultiplexed I/O & Peripheral Pin X6 (General)
26X7I/OMultiplexed I/O & Peripheral Pin X7 (General)
27VDDPowerPower Supply Input (VDD — 4.75 V to 5.25 V)
28VSSGNDGround Reference Pin (VSS)
29VDDPowerPower Supply Input (VDD — 4.75 V to 5.25 V)
30Y0BI/OMultiplexed I/O & Peripheral Pin Y0B (General)
31Y1BI/OMultiplexed I/O & Peripheral Pin Y1B (General)
32Y2BI/OMultiplexed I/O & Peripheral Pin Y2B (General)
33Y3BI/OMultiplexed I/O & Peripheral Pin Y3B (General)
34Y4AI/OMultiplexed I/O & Peripheral Pin Y4A (General)
35Y4BI/OMultiplexed I/O & Peripheral Pin Y4B (General)
36Y5AI/OMultiplexed I/O & Peripheral Pin Y5A (General)
37Y5BI/OMultiplexed I/O & Peripheral Pin Y5B (General)
38VDDPowerPower Supply Input (VDD — 4.75 V to 5.25 V)
39VSSGNDExposed Thermal & Ground Pad (VSS)
40STATUS/ DBG_DATAI/OMultiplexed I/O & Peripheral Pin STATUS/ DBG_DATA (General)
41DRDYI/OMultiplexed I/O & Peripheral Pin DRDY (General)
42VREFAnalogMultiplexed I/O & Peripheral Pin VREF (General)
43S SYNC/_ DBG_CLKI/OMultiplexed I/O & Peripheral Pin S SYNC/_ DBG_CLK (General)
44SSI/OMultiplexed I/O & Peripheral Pin SS (SPI)
PIN 1 MOSI
I/O
Multiplexed I/O & Peripheral Pin MOSI (SPI)
Design note: SPIdatainput
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: AT42QT1481-AU (MICROCHIP · TQFP-44(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
AT42QT1481-AU (TQFP-44(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT42QT1481-AU (TQFP-44(10x10)) - 2. Standard Pinout (Top View)
True package pinout (44 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT42QT1481-AU (TQFP-44(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT42QT1481-AU (TQFP-44(10x10)) - 4. Package Dimensions (D×E×A)
TQFP-44(10x10) · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT42QT1481-AU (TQFP-44(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (44 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT42QT1481-AU (TQFP-44(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for AT42QT1481
P3 · p03_fig011486×1401px
AT42QT1481-AU (TQFP-44(10x10)) — 1. Pinout and Schematic | 1.1 Pinout Configuration | SS | S_SYNC / DBG_CLK | VREF | DRDY | STATUS / DBG_DATA | VSS | VDD | Y5B | Y5A | Y4B | Y4A | SMP | Y3A | Y2A | Y1A | Y0A | VDD | VSS | X0 | X1 | X2 | X3 | MOSI | MISO | SCK | RST | VDD |
1. Pinout and Schematic | 1.1 Pinout Configuration | SS | S_SYNC / DBG_CLK | VREF | DRDY | STATUS / DBG_DATA | VSS | VDD | Y5B | Y5A | Y4B | Y4A | SMP | Y3A | Y2A | Y1A | Y0A | VDD | VSS | X0 | X1 | X2 | X3 | MOSI | MISO | SCK | RST | VDD |
P3 · p03_fig01P3
AT42QT1481-AU (TQFP-44(10x10)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P10 · p10_fig01906×378px
AT42QT1481-AU (TQFP-44(10x10)) — Figure 2-2. VCs - Nonlinear During Burst (Burst too long, or Cs too small, or X-Y transcapacitance too large)
Figure 2-2. VCs - Nonlinear During Burst (Burst too long, or Cs too small, or X-Y transcapacitance too large)
P13 · p13_fig01974×1139px
AT42QT1481-AU (TQFP-44(10x10)) — Figure 2-6. Probing X-Drive Waveforms With a Coin
Figure 2-6. Probing X-Drive Waveforms With a Coin
P13 · p13_fig01P13
AT42QT1481-AU (TQFP-44(10x10)) — Datasheet Page 13 (p13_fig01)
Datasheet Page 13 (p13_fig01)
P60 · p60_fig011963×2316px
AT42QT1481-AU (TQFP-44(10x10)) — 60 AT42QT1481 [DATASHEET]
60 AT42QT1481 [DATASHEET]
P60 · p60_fig01P60
AT42QT1481-AU (TQFP-44(10x10)) — Datasheet Page 60 (p60_fig01)
Datasheet Page 60 (p60_fig01)

Technical Specifications & Part Details (AT42QT1481-AU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT42QT1481-AU (TQFP-44(10x10)) is a 44-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.20 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 4.75 V to 5.25 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI interfaces.
Operating Supply VoltageV_CC / V_DD
4.75 V to 5.25 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
4 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.20 mm (A1=0.10 mm)
Package family: TQFP (TQFP-44(10x10))
Pin Count & Lead PitchN / e
44 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol44 auto-grouped pins
OK
IPC-7351B Land Pattern44 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-44(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.80mm
Pad Size (W × L)Level B
0.50 × 1.50 mm
Pins / Total PadsTopology
44P / 44Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFP-44(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT42QT1481-AU (TQFP-44(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT42QT1481-AU (TQFP-44(10x10))?

Manufactured by MICROCHIP, the AT42QT1481-AU is housed in a TQFP-44(10x10) package with 44 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 4.75 V to 5.25 V. Key pins include: 1 (MOSI: Multiplexed I/O & Peripheral Pin MOSI (SPI)), 2 (MISO: Multiplexed I/O & Peripheral Pin MISO (SPI)), 3 (SCK: Multiplexed I/O & Peripheral Pin SCK (SPI)), 4 (RST: Multiplexed I/O & Peripheral Pin RST (General)), 5 (VDD: Power Supply Input (VDD — 4.75 V to 5.25 V)), 6 (VSS: Ground Reference Pin (VSS)).

What are the IPC-7351B PCB Footprint dimensions for AT42QT1481-AU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT42QT1481-AU (TQFP-44(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 44 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT42QT1481-AU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT42QT1481-AU (MICROCHIP, TQFP-44(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (44 pins) & AT42QT1481 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1MOSIDigital_IOSignal terminal MOSI (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: SPIDATAINPUT. Supported peripheral buses: SPI.
2MISODigital_IOSignal terminal MISO (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: SPIDATAOUTPUT. Supported peripheral buses: SPI.
3SCKDigital_IOSignal terminal SCK (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: SPICLOCKINPUT. Supported peripheral buses: SPI.
4RSTDigital_IOSignal terminal RST (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
5VDDPower_InPrimary positive power supply input (VDD) operating in the 4.75 V to 5.25 V domain (Max rating: 5.25V).
6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
7XT2Digital_IOSignal terminal XT2 (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: XT2. Supported peripheral buses: General.
8XT1Digital_IOSignal terminal XT1 (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: XT1. Supported peripheral buses: General.
9RXDigital_IOSignal terminal RX (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: RX. Supported peripheral buses: UART.
10TXDigital_IOSignal terminal TX (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: TX. Supported peripheral buses: UART.
11WSDigital_IOSignal terminal WS (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: WS. Supported peripheral buses: General.
12SMPDigital_IOSignal terminal SMP (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: SMP. Supported peripheral buses: General.
13Y3ADigital_IOSignal terminal Y3A (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y3A. Supported peripheral buses: General.
14Y2ADigital_IOSignal terminal Y2A (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y2A. Supported peripheral buses: General.
15Y1ADigital_IOSignal terminal Y1A (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y1A. Supported peripheral buses: General.
16Y0ADigital_IOSignal terminal Y0A (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y0A. Supported peripheral buses: General.
17VDDPower_InPrimary positive power supply input (VDD) operating in the 4.75 V to 5.25 V domain (Max rating: 5.25V).
18VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
19X0Digital_IOSignal terminal X0 (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: X0. Supported peripheral buses: General.
20X1Digital_IOSignal terminal X1 (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: X1. Supported peripheral buses: General.
21X2Digital_IOSignal terminal X2 (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: X2. Supported peripheral buses: General.
22X3Digital_IOSignal terminal X3 (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: X3. Supported peripheral buses: General.
23X4Digital_IOSignal terminal X4 (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: X4. Supported peripheral buses: General.
24X5Digital_IOSignal terminal X5 (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: X5. Supported peripheral buses: General.
25X6Digital_IOSignal terminal X6 (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: X6. Supported peripheral buses: General.
26X7Digital_IOSignal terminal X7 (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: X7. Supported peripheral buses: General.
27VDDPower_InPrimary positive power supply input (VDD) operating in the 4.75 V to 5.25 V domain (Max rating: 5.25V).
28VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
29VDDPower_InPrimary positive power supply input (VDD) operating in the 4.75 V to 5.25 V domain (Max rating: 5.25V).
30Y0BDigital_IOSignal terminal Y0B (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y0B. Supported peripheral buses: General.
31Y1BDigital_IOSignal terminal Y1B (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y1B. Supported peripheral buses: General.
32Y2BDigital_IOSignal terminal Y2B (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y2B. Supported peripheral buses: General.
33Y3BDigital_IOSignal terminal Y3B (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y3B. Supported peripheral buses: General.
34Y4ADigital_IOSignal terminal Y4A (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y4A. Supported peripheral buses: General.
35Y4BDigital_IOSignal terminal Y4B (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y4B. Supported peripheral buses: General.
36Y5ADigital_IOSignal terminal Y5A (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y5A. Supported peripheral buses: General.
37Y5BDigital_IOSignal terminal Y5B (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: Y5B. Supported peripheral buses: General.
38VDDPower_InPrimary positive power supply input (VDD) operating in the 4.75 V to 5.25 V domain (Max rating: 5.25V).
39VSSGNDBottom exposed die attach pad (VSS) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
40STATUS/ DBG_DATADigital_IOSignal terminal STATUS/ DBG_DATA (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: STATUS/ DBG_DATA. Supported peripheral buses: General.
41DRDYOpen_DrainSignal terminal DRDY (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: DRDY. Supported peripheral buses: General.
42VREFAnalogSignal terminal VREF (Analog, 4.75 V to 5.25 V domain). Multiplexed alternate functions: VREF. Supported peripheral buses: General.
43S SYNC/_ DBG_CLKDigital_IOSignal terminal S SYNC/_ DBG_CLK (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: S SYNC/_ DBG_CLK. Supported peripheral buses: General.
44SSDigital_IOSignal terminal SS (I/O, 4.75 V to 5.25 V domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI.
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