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AT42QT1050-UUR (WLCSP-12(1.4x1.6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT42QT1050-UUR

MICROCHIPID: C152163WLCSP-12(1.4x1.6) · 12 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT42QT1050-UUR (WLCSP-12(1.4x1.6))A1Key2A3Key0A5Key1B2Key4B4GroundB6PowerD6IOD6D4IOD4D2IOD2C5I2CdatalineC3ConnecttoI2CC1Key3Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.812.77.62.5-2.5-7.6-12.7mm
2. 2D FOOTPRINT
D6D4D2C5C3C1B6B4B2A5A3A1E=1.40mm · Pitch e=0.40mmD=1.60mm-2-10123210-1-2-3mm
3. 3D CAD MODEL
Package Body: 1.40mm × 1.60mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (12/12)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1Key2I/OMultiplexed I/O & Peripheral Pin Key2 (General)
A3Key0I/OMultiplexed I/O & Peripheral Pin Key0 (General)
A5Key1I/OMultiplexed I/O & Peripheral Pin Key1 (General)
B2Key4I/OMultiplexed I/O & Peripheral Pin Key4 (General)
B4GroundI/OMultiplexed I/O & Peripheral Pin Ground (General)
B6PowerI/OMultiplexed I/O & Peripheral Pin Power (General)
C1Key3I/OMultiplexed I/O & Peripheral Pin Key3 (General)
C3ConnecttoI2CclockI/OMultiplexed I/O & Peripheral Pin ConnecttoI2Cclock (I2C)
C5I2CdatalineI/OMultiplexed I/O & Peripheral Pin I2Cdataline (I2C)
D2IOD2I/OGeneral Purpose Digital I/O Pin IOD2
D4IOD4I/OGeneral Purpose Digital I/O Pin IOD4
D6IOD6I/OGeneral Purpose Digital I/O Pin IOD6
PIN A1 Key2
I/O
Multiplexed I/O & Peripheral Pin Key2 (General)
Design note: KEY2
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: AT42QT1050-UUR (MICROCHIP · WLCSP-12(1.4x1.6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
AT42QT1050-UUR (WLCSP-12(1.4x1.6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT42QT1050-UUR (WLCSP-12(1.4x1.6)) - 2. Standard Pinout (Top View)
True package pinout (12 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT42QT1050-UUR (WLCSP-12(1.4x1.6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT42QT1050-UUR (WLCSP-12(1.4x1.6)) - 4. Package Dimensions (D×E×A)
WLCSP-12(1.4x1.6) · 1.40×1.60mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT42QT1050-UUR (WLCSP-12(1.4x1.6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (12 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT42QT1050-UUR (WLCSP-12(1.4x1.6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for AT42QT1050
P2 · p02_fig01EXACT PACKAGE
AT42QT1050-UUR (WLCSP-12(1.4x1.6)) — 2
2
P2 · p02_fig021472×1068px
AT42QT1050-UUR (WLCSP-12(1.4x1.6)) — C
C
P2 · p02_fig01P2
AT42QT1050-UUR (WLCSP-12(1.4x1.6)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P28 · p28_fig011954×2430px
AT42QT1050-UUR (WLCSP-12(1.4x1.6)) — 28 AT42QT1050 [PRELIMINARY DATASHEET]
28 AT42QT1050 [PRELIMINARY DATASHEET]

Technical Specifications & Part Details (AT42QT1050-UUR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT42QT1050-UUR (WLCSP-12(1.4x1.6)) is a 12-pin standard electronic & interconnect component featuring a 1.60 × 1.40 × 0.50 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8 V to 5.5 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8 V to 5.5 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
400 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
1.60 × 1.40 × 0.50 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-12(1.4x1.6))
Pin Count & Lead PitchN / e
12 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol12 auto-grouped pins
OK
IPC-7351B Land Pattern12 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WLCSP-12(1.4x1.6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
1.60 × 1.40 mm
Height (A) & Pitch (e)IPC-7351B
A=0.50mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
12P / 12Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-12(1.4x1.6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT42QT1050-UUR (WLCSP-12(1.4x1.6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT42QT1050-UUR (WLCSP-12(1.4x1.6))?

Manufactured by MICROCHIP, the AT42QT1050-UUR is housed in a WLCSP-12(1.4x1.6) package with 12 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.8 V to 5.5 V. Key pins include: A1 (Key2: Multiplexed I/O & Peripheral Pin Key2 (General)), A3 (Key0: Multiplexed I/O & Peripheral Pin Key0 (General)), A5 (Key1: Multiplexed I/O & Peripheral Pin Key1 (General)), B2 (Key4: Multiplexed I/O & Peripheral Pin Key4 (General)), B4 (Ground: Multiplexed I/O & Peripheral Pin Ground (General)), B6 (Power: Multiplexed I/O & Peripheral Pin Power (General)).

What are the IPC-7351B PCB Footprint dimensions for AT42QT1050-UUR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT42QT1050-UUR (WLCSP-12(1.4x1.6)) has a nominal body envelope of 1.40 × 1.60 mm, pitch e = 0.40 mm, and 12 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT42QT1050-UUR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT42QT1050-UUR (MICROCHIP, WLCSP-12(1.4x1.6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (12 pins) & AT42QT1050 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1Key2Digital_IOSignal terminal Key2 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Key2. Supported peripheral buses: General.
A3Key0Digital_IOSignal terminal Key0 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Key0. Supported peripheral buses: General.
A5Key1Digital_IOSignal terminal Key1 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Key1. Supported peripheral buses: General.
B2Key4Digital_IOSignal terminal Key4 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Key4. Supported peripheral buses: General.
B4GroundDigital_IOSignal terminal Ground (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Ground. Supported peripheral buses: General.
B6PowerDigital_IOSignal terminal Power (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Power. Supported peripheral buses: General.
C1Key3Digital_IOSignal terminal Key3 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Key3. Supported peripheral buses: General.
C3ConnecttoI2CclockDigital_IOSignal terminal ConnecttoI2Cclock (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: ConnecttoI2Cclock. Supported peripheral buses: I2C.
C5I2CdatalineDigital_IOSignal terminal I2Cdataline (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: I2Cdataline. Supported peripheral buses: I2C.
D2IOD2Digital_IOGeneral Purpose Digital I/O Pin IOD2
D4IOD4Digital_IOGeneral Purpose Digital I/O Pin IOD4
D6IOD6Digital_IOGeneral Purpose Digital I/O Pin IOD6
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