QFN-28-EP(6x6) · 29P
29P6.0×6.0×1.00mmP=0.65mm
PIC32MM0016G (QFN-28-EP(6x6))
Synchronized Pinout (Symbol / 2D / 3D) (29/29)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | PGED1/RP14/RB0 | I/O | Multiplexed I/O & Peripheral Pin PGED1/RP14/RB0 (General) |
| 2 | IO2 | I/O | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | PIC32MM0016GPL036 | I/O | Multiplexed I/O & Peripheral Pin PIC32MM0016GPL036 (General) |
| 5 | IO2 | I/O | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | TDI/AN8/RP13/RB13 | I/O | Multiplexed I/O & Peripheral Pin TDI/AN8/RP13/RB13 (General) |
| 7 | NC | NC | No Connect (Leave Floating) |
| 8 | PIC32MM0064GPL036 | I/O | Multiplexed I/O & Peripheral Pin PIC32MM0064GPL036 (General) |
| 9 | AVSS/VSS | GND | Ground Reference Pin (AVSS/VSS) |
| 10 | AVDD/VDD | Power | Power Supply Input (AVDD/VDD — 3.3V / 5.0V Standard Logic) |
| 11 | IO6 | I/O | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | IO7 | I/O | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | AVSS | GND | Ground Reference Pin (AVSS) |
| 14 | AVDD | Power | Power Supply Input (AVDD — 3.3V / 5.0V Standard Logic) |
| 15 | MCLR | I/O | Multiplexed I/O & Peripheral Pin MCLR (General) |
| 16 | IO18 | I/O | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
| 17 | IO8 | I/O | GPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1 |
| 18 | IO19 | I/O | GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8 |
| 19 | IO20 | I/O | GPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9 |
| 20 | N/C | I/O | Multiplexed I/O & Peripheral Pin N/C (General) |
| 21 | RP13/RB13 | I/O | Multiplexed I/O & Peripheral Pin RP13/RB13 (General) |
| 22 | RP9/RB14 | I/O | Multiplexed I/O & Peripheral Pin RP9/RB14 (General) |
| 23 | RP10/RB15 | I/O | Multiplexed I/O & Peripheral Pin RP10/RB15 (General) |
| 24 | AVSS | GND | Ground Reference Pin (AVSS) |
| 25 | AVDD | Power | Power Supply Input (AVDD — 3.3V / 5.0V Standard Logic) |
| 26 | MCLR# | I/O | Multiplexed I/O & Peripheral Pin MCLR# (General) |
| 27 | RP1/RA0 | I/O | Multiplexed I/O & Peripheral Pin RP1/RA0 (General) |
| 28 | RP2/RA1 | I/O | Multiplexed I/O & Peripheral Pin RP2/RA1 (General) |
| 29 | EPAD | GND | Exposed Thermal & Ground Pad (EPAD) |
PIN 1 PGED1/RP14/RB0
I/OMultiplexed I/O & Peripheral Pin PGED1/RP14/RB0 (General)
Design note: Signal terminal PGED1/RP14/RB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PGED1/RP14/RB0. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for PIC32MM0016G
P1 · p01_fig01376×200px
P4 · p04_fig01982×793px
P6 · p06_fig011149×865px
P7 · p07_fig011777×1637px
P7 · p07_fig01P7
P249 · p249_fig011791×2723px
P249 · p249_fig01P249
P250 · p250_fig011791×2723px
P250 · p250_fig01P250
P252 · p252_fig011791×2723px
P253 · p253_fig011791×2723px
P267 · p267_fig011781×2529px
Page 1 / 2 (14 extracted figures)
Technical Specifications & Part Details (PIC32MM0016GPL028-I/ML)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:PIC32MM0016GPL028-I/ML (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2S, ADC, PWM, JTAG / SWD, IrDA, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(6x6))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2S, ADC, PWM, JTAG / SWD, IrDA, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol29 auto-grouped pins
IPC-7351B Land Pattern29 pads · Pitch 0.65mm
IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — PIC32MM0016G (2)
QFN-36-EP(6x6) · 37P
37P6.0×6.0×1.00mmP=0.5mm
PIC32MM0016G (QFN-36-EP(6x6))
Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.65mm
Pad Size (W × L)Level B
0.36 × 0.85 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-28-EP(6x6) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — PIC32MM0016GPL028-I/ML (QFN-28-EP(6x6))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of PIC32MM0016GPL028-I/ML (QFN-28-EP(6x6))?
Manufactured by MICROCHIP, the PIC32MM0016GPL028-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.65 mm lead pitch. Key pins include: 1 (PGED1/RP14/RB0: Multiplexed I/O & Peripheral Pin PGED1/RP14/RB0 (General)), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (PIC32MM0016GPL036: Multiplexed I/O & Peripheral Pin PIC32MM0016GPL036 (General)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (TDI/AN8/RP13/RB13: Multiplexed I/O & Peripheral Pin TDI/AN8/RP13/RB13 (General)).
What are the IPC-7351B PCB Footprint dimensions for PIC32MM0016GPL028-I/ML?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC32MM0016GPL028-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.65 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC32MM0016GPL028-I/ML?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC32MM0016GPL028-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (29 pins) & PIC32MM0016G Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PGED1/RP14/RB0 | Digital_IO | Signal terminal PGED1/RP14/RB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PGED1/RP14/RB0. Supported peripheral buses: General. |
| 2 | IO2 | Digital_IO | General Purpose Digital I/O Pin IO2 |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | PIC32MM0016GPL036 | Digital_IO | Signal terminal PIC32MM0016GPL036 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIC32MM0016GPL036. Supported peripheral buses: General. |
| 5 | IO2 | Digital_IO | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | TDI/AN8/RP13/RB13 | Digital_IO | Signal terminal TDI/AN8/RP13/RB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TDI/AN8/RP13/RB13. Supported peripheral buses: General. |
| 7 | NC | No_Connect | No Connect (Leave Floating) |
| 8 | PIC32MM0064GPL036 | Digital_IO | Signal terminal PIC32MM0064GPL036 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIC32MM0064GPL036. Supported peripheral buses: General. |
| 9 | AVSS/VSS | GND | 0V electrical ground return terminal (AVSS/VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 10 | AVDD/VDD | Power_In | Primary positive power supply input (AVDD/VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 11 | IO6 | Digital_IO | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | IO7 | Digital_IO | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | AVSS | GND | 0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 14 | AVDD | Power_In | Primary positive power supply input (AVDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 15 | MCLR | Digital_IO | Signal terminal MCLR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MCLR. Supported peripheral buses: General. |
| 16 | IO18 | Digital_IO | GPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3 |
| 17 | IO8 | Digital_IO | GPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1 |
| 18 | IO19 | Digital_IO | GPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8 |
| 19 | IO20 | Digital_IO | GPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9 |
| 20 | N/C | Digital_IO | Signal terminal N/C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: U1RTS. Supported peripheral buses: General. |
| 21 | RP13/RB13 | Digital_IO | Signal terminal RP13/RB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP13/RB13. Supported peripheral buses: General. |
| 22 | RP9/RB14 | Digital_IO | Signal terminal RP9/RB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP9/RB14. Supported peripheral buses: General. |
| 23 | RP10/RB15 | Digital_IO | Signal terminal RP10/RB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP10/RB15. Supported peripheral buses: General. |
| 24 | AVSS | GND | 0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 25 | AVDD | Power_In | Primary positive power supply input (AVDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 26 | MCLR# | Digital_IO | Signal terminal MCLR# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General. |
| 27 | RP1/RA0 | Digital_IO | Signal terminal RP1/RA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP1/RA0. Supported peripheral buses: General. |
| 28 | RP2/RA1 | Digital_IO | Signal terminal RP2/RA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP2/RA1. Supported peripheral buses: General. |
| 29 | EPAD | GND | Bottom exposed die attach pad (EPAD) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |