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PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC32MM0016GPL036-I/M2

MICROCHIPID: C150774QFN-36-EP(6x6) · 37 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6))1RP16/RB22IO233V34PIC32MM0016G5IO26TDI/AN8/RP137NC8PIC32MM0064G9AVSS/VSS10AVDD/VDD11IO612IO713AVSS14AVDD15MCLR16IO1817IO818IO1919IO2037EPAD36PGEC1/RP15/R35PGED1/RP14/R34RP2/RA133RP1/RA032MCLR#31AVDD30AVSS29RP10/RB1528RP9/RB1427RP13/RB1326RP12/RB1225PGEC2/RP18/R24PGED2/RP17/R23VDD22VCAP21RP19/RC920N/CGrid Pitch = 2.54mm (IEEE-315)-20.3-15.2-10.2-5.105.110.215.220.330.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637E=6.00mm · Pitch e=0.50mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (37/37)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RP16/RB2I/OMultiplexed I/O & Peripheral Pin RP16/RB2 (General)
2IO2I/OGeneral Purpose Digital I/O Pin IO2
33V3Power3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4PIC32MM0016GPL036I/OMultiplexed I/O & Peripheral Pin PIC32MM0016GPL036 (General)
5IO2I/OGPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1
6TDI/AN8/RP13/RB13I/OMultiplexed I/O & Peripheral Pin TDI/AN8/RP13/RB13 (General)
7NCNCNo Connect (Leave Floating)
8PIC32MM0064GPL036I/OMultiplexed I/O & Peripheral Pin PIC32MM0064GPL036 (General)
9AVSS/VSSGNDGround Reference Pin (AVSS/VSS)
10AVDD/VDDPowerPower Supply Input (AVDD/VDD — 3.3V / 5.0V Standard Logic)
11IO6I/OGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12IO7I/OGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13AVSSGNDGround Reference Pin (AVSS)
14AVDDPowerPower Supply Input (AVDD — 3.3V / 5.0V Standard Logic)
15MCLRI/OMultiplexed I/O & Peripheral Pin MCLR (General)
16IO18I/OGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17IO8I/OGPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1
18IO19I/OGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20I/OGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20N/CI/OMultiplexed I/O & Peripheral Pin N/C (General)
21RP19/RC9I/OMultiplexed I/O & Peripheral Pin RP19/RC9 (General)
22VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
23VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
24PGED2/RP17/RB10I/OMultiplexed I/O & Peripheral Pin PGED2/RP17/RB10 (General)
25PGEC2/RP18/RB11I/OMultiplexed I/O & Peripheral Pin PGEC2/RP18/RB11 (General)
26RP12/RB12I/OMultiplexed I/O & Peripheral Pin RP12/RB12 (General)
27RP13/RB13I/OMultiplexed I/O & Peripheral Pin RP13/RB13 (General)
28RP9/RB14I/OMultiplexed I/O & Peripheral Pin RP9/RB14 (General)
29RP10/RB15I/OMultiplexed I/O & Peripheral Pin RP10/RB15 (General)
30AVSSGNDGround Reference Pin (AVSS)
31AVDDPowerPower Supply Input (AVDD — 3.3V / 5.0V Standard Logic)
32MCLR#I/OMultiplexed I/O & Peripheral Pin MCLR# (General)
33RP1/RA0I/OMultiplexed I/O & Peripheral Pin RP1/RA0 (General)
34RP2/RA1I/OMultiplexed I/O & Peripheral Pin RP2/RA1 (General)
35PGED1/RP14/RB0I/OMultiplexed I/O & Peripheral Pin PGED1/RP14/RB0 (General)
36PGEC1/RP15/RB1I/OMultiplexed I/O & Peripheral Pin PGEC1/RP15/RB1 (General)
37EPADGNDExposed Thermal & Ground Pad (EPAD)
PIN 1 RP16/RB2
I/O
Multiplexed I/O & Peripheral Pin RP16/RB2 (General)
Design note: Signal terminal RP16/RB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP16/RB2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC32MM0016GPL036-I/M2 (MICROCHIP · QFN-36-EP(6x6))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) - 2. Standard Pinout (Top View)
True package pinout (37 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) - 4. Package Dimensions (D×E×A)
QFN-36-EP(6x6) · 6.00×6.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (37 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for PIC32MM0016G
P1 · p01_fig01376×200px
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) — 采用MIPS32® microAptiv™ UC 内核的低功耗
采用MIPS32® microAptiv™ UC 内核的低功耗
P4 · p04_fig01982×793px
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) — PGEC1/RP15/RB1 | RP16/RB2 | CLKI/RP3/RA2 | CLKO/RP4/RA3(1) | PGED1/RP14/RB0 | PGED3/SOSCI/RP5/RB4 | PGEC3/SOSCO/RP6/RA4 | RP11/RB7 | RP7/RB8(1) | RP8/RB9(1) | RP12/RB12 | RP13/RB13 | VCAP | RP9/RB14 | RP10/RB15(1) | AVSS/VSS | PGEC2/RP1/RA0
PGEC1/RP15/RB1 | RP16/RB2 | CLKI/RP3/RA2 | CLKO/RP4/RA3(1) | PGED1/RP14/RB0 | PGED3/SOSCI/RP5/RB4 | PGEC3/SOSCO/RP6/RA4 | RP11/RB7 | RP7/RB8(1) | RP8/RB9(1) | RP12/RB12 | RP13/RB13 | VCAP | RP9/RB14 | RP10/RB15(1) | AVSS/VSS | PGEC2/RP1/RA0
P6 · p06_fig011149×865px
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) — 图注：阴影引脚最高可承受5V 电压。 注1：引脚具有更高的电流驱动能力。详情请参见第26.0 节“电气特性”。
图注：阴影引脚最高可承受5V 电压。 注1：引脚具有更高的电流驱动能力。详情请参见第26.0 节“电气特性”。
P7 · p07_fig011777×1637px
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) — 引脚 功能 引脚 功能
引脚 功能 引脚 功能
P7 · p07_fig01P7
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) — Datasheet Page 7 (p07_fig01)
Datasheet Page 7 (p07_fig01)
P249 · p249_fig011791×2723px
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) —  2017 Microchip Technology Inc. DS60001324B_CN 第249 页 | PIC32MM0064GPL036 系列 | Microchip Technology Drawing C04-333-M6 Rev A Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at
 2017 Microchip Technology Inc. DS60001324B_CN 第249 页 | PIC32MM0064GPL036 系列 | Microchip Technology Drawing C04-333-M6 Rev A Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at
P250 · p250_fig011791×2723px
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) — PIC32MM0064GPL036 系列 | DS60001324B_CN 第250 页  2017 Microchip Technology Inc. | RECOMMENDED LAND PATTERN | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
PIC32MM0064GPL036 系列 | DS60001324B_CN 第250 页  2017 Microchip Technology Inc. | RECOMMENDED LAND PATTERN | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
P252 · p252_fig011791×2723px
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) — PIC32MM0064GPL036 系列 | DS60001324B_CN 第252 页  2017 Microchip Technology Inc. | Microchip Technology Drawing C04-272B-M2 Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at http:
PIC32MM0064GPL036 系列 | DS60001324B_CN 第252 页  2017 Microchip Technology Inc. | Microchip Technology Drawing C04-272B-M2 Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at http:
P252 · p252_fig01P252
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) — Datasheet Page 252 (p252_fig01)
Datasheet Page 252 (p252_fig01)
P253 · p253_fig011791×2723px
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) —  2017 Microchip Technology Inc. DS60001324B_CN 第253 页 | PIC32MM0064GPL036 系列 | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Optional Center Pad Width | Contact Pad Spacing | Optional Center Pad Length | Contact Pitch | Y2 X2
 2017 Microchip Technology Inc. DS60001324B_CN 第253 页 | PIC32MM0064GPL036 系列 | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Optional Center Pad Width | Contact Pad Spacing | Optional Center Pad Length | Contact Pitch | Y2 X2
P253 · p253_fig01P253
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) — Datasheet Page 253 (p253_fig01)
Datasheet Page 253 (p253_fig01)
P267 · p267_fig011781×2529px
PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) —  2017 Microchip Technology Inc. DS60001324B_CN 第267 页 | 提供本文档的中文版本仅为了便于理解。请勿忽视文档中包含 的英文部分，因为其中提供了有关Microchip 产品性能和使用 情况的有用信息。Microchip Technology Inc. 及其分公司和相 关公司、各级主管与员工及事务代理机构对译文中可能存在的 任何差错不承担任何责任。建议参考Microchip Technology Inc. 的英文原版文档。 |
 2017 Microchip Technology Inc. DS60001324B_CN 第267 页 | 提供本文档的中文版本仅为了便于理解。请勿忽视文档中包含 的英文部分，因为其中提供了有关Microchip 产品性能和使用 情况的有用信息。Microchip Technology Inc. 及其分公司和相 关公司、各级主管与员工及事务代理机构对译文中可能存在的 任何差错不承担任何责任。建议参考Microchip Technology Inc. 的英文原版文档。 |
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (PIC32MM0016GPL036-I/M2)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) is a 36-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2S, ADC, PWM, JTAG / SWD, IrDA, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-36-EP(6x6))
Pin Count & Lead PitchN / e
36 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2S, ADC, PWM, JTAG / SWD, IrDA, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol37 auto-grouped pins
OK
IPC-7351B Land Pattern37 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.95×3.95mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-36-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.90 mm
Pins / Total PadsTopology
37P / 37Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-36-EP(6x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6))?

Manufactured by MICROCHIP, the PIC32MM0016GPL036-I/M2 is housed in a QFN-36-EP(6x6) package with 37 pins and a 0.50 mm lead pitch. Key pins include: 1 (RP16/RB2: Multiplexed I/O & Peripheral Pin RP16/RB2 (General)), 2 (IO2: General Purpose Digital I/O Pin IO2), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (PIC32MM0016GPL036: Multiplexed I/O & Peripheral Pin PIC32MM0016GPL036 (General)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (TDI/AN8/RP13/RB13: Multiplexed I/O & Peripheral Pin TDI/AN8/RP13/RB13 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC32MM0016GPL036-I/M2?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC32MM0016GPL036-I/M2 (QFN-36-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.50 mm, and 37 copper pads plus a central exposed thermal pad (EPAD) of 3.95 × 3.95 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC32MM0016GPL036-I/M2?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC32MM0016GPL036-I/M2 (MICROCHIP, QFN-36-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (37 pins) & PIC32MM0016G Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RP16/RB2Digital_IOSignal terminal RP16/RB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP16/RB2. Supported peripheral buses: General.
2IO2Digital_IOGeneral Purpose Digital I/O Pin IO2
33V3Power_In3.3V Main Power Supply Rail (3.0V ~ 3.6V)
4PIC32MM0016GPL036Digital_IOSignal terminal PIC32MM0016GPL036 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIC32MM0016GPL036. Supported peripheral buses: General.
5IO2Digital_IOGPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1
6TDI/AN8/RP13/RB13Digital_IOSignal terminal TDI/AN8/RP13/RB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TDI/AN8/RP13/RB13. Supported peripheral buses: General.
7NCNo_ConnectNo Connect (Leave Floating)
8PIC32MM0064GPL036Digital_IOSignal terminal PIC32MM0064GPL036 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PIC32MM0064GPL036. Supported peripheral buses: General.
9AVSS/VSSGND0V electrical ground return terminal (AVSS/VSS) for internal core logic, I/O drivers, and analog sub-blocks.
10AVDD/VDDPower_InPrimary positive power supply input (AVDD/VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
11IO6Digital_IOGPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5
12IO7Digital_IOGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
14AVDDPower_InPrimary positive power supply input (AVDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
15MCLRDigital_IOSignal terminal MCLR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MCLR. Supported peripheral buses: General.
16IO18Digital_IOGPIO18 / RTC_GPIO18 / U1RXD / ADC2_CH7 / CLK_OUT3
17IO8Digital_IOGPIO8 / RTC_GPIO8 / TOUCH8 / ADC1_CH7 / SUBSPICS1
18IO19Digital_IOGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20Digital_IOGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20N/CDigital_IOSignal terminal N/C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: U1RTS. Supported peripheral buses: General.
21RP19/RC9Digital_IOSignal terminal RP19/RC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP19/RC9. Supported peripheral buses: General.
22VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
23VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24PGED2/RP17/RB10Digital_IOSignal terminal PGED2/RP17/RB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PGED2/RP17/RB10. Supported peripheral buses: General.
25PGEC2/RP18/RB11Digital_IOSignal terminal PGEC2/RP18/RB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PGEC2/RP18/RB11. Supported peripheral buses: General.
26RP12/RB12Digital_IOSignal terminal RP12/RB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP12/RB12. Supported peripheral buses: General.
27RP13/RB13Digital_IOSignal terminal RP13/RB13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP13/RB13. Supported peripheral buses: General.
28RP9/RB14Digital_IOSignal terminal RP9/RB14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP9/RB14. Supported peripheral buses: General.
29RP10/RB15Digital_IOSignal terminal RP10/RB15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP10/RB15. Supported peripheral buses: General.
30AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
31AVDDPower_InPrimary positive power supply input (AVDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
32MCLR#Digital_IOSignal terminal MCLR# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: MCLR#. Supported peripheral buses: General.
33RP1/RA0Digital_IOSignal terminal RP1/RA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP1/RA0. Supported peripheral buses: General.
34RP2/RA1Digital_IOSignal terminal RP2/RA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RP2/RA1. Supported peripheral buses: General.
35PGED1/RP14/RB0Digital_IOSignal terminal PGED1/RP14/RB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PGED1/RP14/RB0. Supported peripheral buses: General.
36PGEC1/RP15/RB1Digital_IOSignal terminal PGEC1/RP15/RB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PGEC1/RP15/RB1. Supported peripheral buses: General.
37EPADGNDBottom exposed die attach pad (EPAD) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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