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ATMEGA328P-AU (TQFP-32(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATMEGA328P-AU

MICROCHIPID: C14877TQFP-32(7x7) · 32 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATMEGA328P-AU (TQFP-32(7x7))1PD32PD43GND4VCC5GND6VCC7PB68PB79PD510PD611PD712PB013PB114PB215PB316PB432PD231PD130PD029PC6/RESET28PC527PC426PC325PC224PC123PC022ADC721GND20AREF19ADC618AVCC17PB5Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132E=7.00mm · Pitch e=0.80mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (32/32)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PD3I/OMultiplexed I/O & Peripheral Pin PD3 (PWM)
2PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART)
3GNDGNDGround Reference Pin (GND)
4VCCPowerPower Supply Input (VCC — 1.8V ~ 5.5V VCC)
5GNDGNDGround Reference Pin (GND)
6VCCPowerPower Supply Input (VCC — 1.8V ~ 5.5V VCC)
7PB6I/OMultiplexed I/O & Peripheral Pin PB6 (RTC/CLK)
8PB7I/OMultiplexed I/O & Peripheral Pin PB7 (RTC/CLK)
9PD5I/OMultiplexed I/O & Peripheral Pin PD5 (PWM)
10PD6I/OMultiplexed I/O & Peripheral Pin PD6 (ADC, PWM)
11PD7I/OMultiplexed I/O & Peripheral Pin PD7 (ADC)
12PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
13PB1I/OMultiplexed I/O & Peripheral Pin PB1 (PWM)
14PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI, PWM)
15PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, PWM)
16PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI)
17PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI)
18AVCCPowerPower Supply Input (AVCC — 1.8V ~ 5.5V VCC)
19ADC6IInput-Only Pin ADC6 (ADC)
20AREFI/OMultiplexed I/O & Peripheral Pin AREF (ADC)
21GNDGNDGround Reference Pin (GND)
22ADC7IInput-Only Pin ADC7 (ADC)
23PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
24PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
25PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
26PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
27PC4I/OMultiplexed I/O & Peripheral Pin PC4 (I2C, ADC)
28PC5I/OMultiplexed I/O & Peripheral Pin PC5 (I2C, ADC)
29PC6/RESETISystem Enable & Hardware Reset (PC6/RESET)
30PD0I/OMultiplexed I/O & Peripheral Pin PD0 (UART)
31PD1I/OMultiplexed I/O & Peripheral Pin PD1 (UART)
32PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
PIN 1 PD3
I/O
Multiplexed I/O & Peripheral Pin PD3 (PWM)
Design note: Port D3 / External Interrupt 1 (INT1) / Timer2 PWM OC2B
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATMEGA328P-AU (MICROCHIP · TQFP-32(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATMEGA328P-AU (TQFP-32(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATMEGA328P-AU (TQFP-32(7x7)) - 2. Standard Pinout (Top View)
True package pinout (32 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATMEGA328P-AU (TQFP-32(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATMEGA328P-AU (TQFP-32(7x7)) - 4. Package Dimensions (D×E×A)
TQFP-32(7x7) · 7.00×7.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATMEGA328P-AU (TQFP-32(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (32 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATMEGA328P-AU (TQFP-32(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for ATMEGA328P
P20 · p20_fig01EXACT PACKAGE
ATMEGA328P-AU (TQFP-32(7x7)) — 20 ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]
20 ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]
P2 · p02_fig011568×1579px
ATMEGA328P-AU (TQFP-32(7x7)) — Figure 1-1. Pinout ATmega48A/PA/88A/PA/168A/PA/328/P
Figure 1-1. Pinout ATmega48A/PA/88A/PA/168A/PA/328/P
P20 · p20_fig01P20
ATMEGA328P-AU (TQFP-32(7x7)) — Datasheet Page 20 (p20_fig01)
Datasheet Page 20 (p20_fig01)
P21 · p21_fig011868×2069px
ATMEGA328P-AU (TQFP-32(7x7)) — 21 ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]
21 ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]
P22 · p22_fig01P22
ATMEGA328P-AU (TQFP-32(7x7)) — Datasheet Page 22 (p22_fig01)
Datasheet Page 22 (p22_fig01)
P24 · p24_fig01P24
ATMEGA328P-AU (TQFP-32(7x7)) — Datasheet Page 24 (p24_fig01)
Datasheet Page 24 (p24_fig01)
P23 · p23_fig01All Packages in PDF
ATMEGA328P-AU (TQFP-32(7x7)) — 9.4 32M1-A
9.4 32M1-A

Technical Specifications & Part Details (ATMEGA328P-AU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:ATMEGA328P-AU (TQFP-32(7x7)) is a 32-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.00 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.8V ~ 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
32 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.00 mm (A1=0.00 mm)
Package family: TQFP (TQFP-32(7x7))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PC6/RESET): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol32 auto-grouped pins
OK
IPC-7351B Land Pattern32 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-32(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.80mm
Pad Size (W × L)Level B
0.50 × 1.50 mm
Pins / Total PadsTopology
32P / 32Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2
BOM
2× 100nF 50V X7R
0402 / 0603
VCC (Pins 4, 6) & AVCC (Pin 18) decoupling — Pin 18 (AVCC) must be powered even if ADC is unused.
C3
BOM
100nF 50V X7R
0402 / 0603
ADC reference filter cap on AREF (Pin 20) — never tie AREF directly to VCC when using internal reference.
R1 + C4
BOM
10kΩ Pull-up + 100nF DTR Cap
0603
Reset & auto-bootloader circuit on PC6/RESET (Pin 29) — couple 100nF in series from DTR# to Pin 29.
Y1 + C5, C6
BOM
16MHz Crystal + 2× 22pF NP0
SMD-3225 + 0603
Main clock crystal (Pin 7 XTAL1, Pin 8 XTAL2) — 16MHz requires VCC >= 4.5V (use <= 8MHz at 3.3V).
ATMEGA328PB-AU
Microchip
Pin-to-Pin TQFP-32(7x7)TQFP-32 pin-compatible MCU family alternative (check Pins 3 & 6 power/GPIO differences on 328PB).
ATMEGA168PA-AU
Microchip
100% Drop-in TQFP-32 (16KB Flash)TQFP-32 pin-compatible MCU family alternative (check Pins 3 & 6 power/GPIO differences on 328PB).

Technical Frequently Asked Questions (FAQ) — ATMEGA328P-AU (TQFP-32(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATMEGA328P-AU (TQFP-32(7x7))?

Manufactured by MICROCHIP, the ATMEGA328P-AU is housed in a TQFP-32(7x7) package with 32 pins and a 0.80 mm lead pitch. Key pins include: 1 (PD3: Multiplexed I/O & Peripheral Pin PD3 (PWM)), 2 (PD4: Multiplexed I/O & Peripheral Pin PD4 (UART)), 3 (GND: Ground Reference Pin (GND)), 4 (VCC: Power Supply Input (VCC — 1.8V ~ 5.5V VCC)), 5 (GND: Ground Reference Pin (GND)), 6 (VCC: Power Supply Input (VCC — 1.8V ~ 5.5V VCC)).

What are the IPC-7351B PCB Footprint dimensions for ATMEGA328P-AU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATMEGA328P-AU (TQFP-32(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.80 mm, and 32 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATMEGA328P-AU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATMEGA328P-AU (MICROCHIP, TQFP-32(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (32 pins) & ATMEGA328P Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PD3Digital_IOSignal terminal PD3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: INT1, OC2B, PCINT19. Supported peripheral buses: PWM.
2PD4Digital_IOSignal terminal PD4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: XCK, T0, PCINT20. Supported peripheral buses: UART.
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4VCCPower_InPrimary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
5GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
6VCCPower_InPrimary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
7PB6Digital_IOSignal terminal PB6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: XTAL1, TOSC1, PCINT6. Supported peripheral buses: RTC/CLK.
8PB7Digital_IOSignal terminal PB7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: XTAL2, TOSC2, PCINT7. Supported peripheral buses: RTC/CLK.
9PD5Digital_IOSignal terminal PD5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: T1, OC0B, PCINT21. Supported peripheral buses: PWM.
10PD6Digital_IOSignal terminal PD6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: AIN0, OC0A, PCINT22. Supported peripheral buses: ADC, PWM.
11PD7Digital_IOSignal terminal PD7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: AIN1, PCINT23. Supported peripheral buses: ADC.
12PB0Digital_IOSignal terminal PB0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: ICP1, CLKO, PCINT0. Supported peripheral buses: General.
13PB1Digital_IOSignal terminal PB1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: OC1A, PCINT1. Supported peripheral buses: PWM.
14PB2Digital_IOSignal terminal PB2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: SS, OC1B, PCINT2, SPI_SLAVE. Supported peripheral buses: SPI, PWM.
15PB3Digital_IOSignal terminal PB3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: MOSI, OC2A, PCINT3, SPI_MASTER. Supported peripheral buses: SPI, PWM.
16PB4Digital_IOSignal terminal PB4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: MISO, PCINT4, SPI_MASTER. Supported peripheral buses: SPI.
17PB5Digital_IOSignal terminal PB5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: SCK, PCINT5, SPI_BUS. Supported peripheral buses: SPI.
18AVCCPower_InPrimary positive power supply input (AVCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
19ADC6AnalogSignal terminal ADC6 (I, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: ADC6. Supported peripheral buses: ADC.
20AREFAnalogSignal terminal AREF (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: ADC_REF. Supported peripheral buses: ADC.
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
22ADC7AnalogSignal terminal ADC7 (I, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: ADC7. Supported peripheral buses: ADC.
23PC0AnalogSignal terminal PC0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: ADC0, PCINT8. Supported peripheral buses: ADC.
24PC1AnalogSignal terminal PC1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: ADC1, PCINT9. Supported peripheral buses: ADC.
25PC2AnalogSignal terminal PC2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: ADC2, PCINT10. Supported peripheral buses: ADC.
26PC3AnalogSignal terminal PC3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: ADC3, PCINT11. Supported peripheral buses: ADC.
27PC4AnalogSignal terminal PC4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: ADC4, SDA, PCINT12, I2C_TWO. Supported peripheral buses: I2C, ADC.
28PC5AnalogSignal terminal PC5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: ADC5, SCL, PCINT13, I2C_TWO. Supported peripheral buses: I2C, ADC.
29PC6/RESETDigital_IOActive-low hardware reset terminal (PC6/RESET): pulling this pin Low resets the processor core and peripherals.
30PD0Digital_IOSignal terminal PD0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: RXD, PCINT16. Supported peripheral buses: UART.
31PD1Digital_IOSignal terminal PD1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: TXD, PCINT17. Supported peripheral buses: UART.
32PD2Digital_IOSignal terminal PD2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: INT0, PCINT18. Supported peripheral buses: General.
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