Mechanical Dimensions & Land Pattern (SOIC-8-EP)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SOIC-8-EP | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — MIC5280YME (SOIC-8-EP)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of MIC5280YME (SOIC-8-EP)?
Manufactured by MICROCHIP, the MIC5280YME is housed in a SOIC-8-EP package with 9 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 4.5V to 120V. Key pins include: 1 (CBYP: Multiplexed I/O & Peripheral Pin CBYP (General)), 2 (VOUT: Regulated Power Output (VOUT — 4.5V to 120V)), 3 (ADJ: Multiplexed I/O & Peripheral Pin ADJ (General)), 4 (GND: Ground Reference Pin (GND)), 5 (EN: System Enable & Hardware Reset (EN)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).
What are the IPC-7351B PCB Footprint dimensions for MIC5280YME?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MIC5280YME (SOIC-8-EP) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 9 copper pads plus a central exposed thermal pad (EPAD) of 2.00 × 2.00 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MIC5280YME?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MIC5280YME (MICROCHIP, SOIC-8-EP) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (9 pins) & MIC5280 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | CBYP | Digital_IO | Signal terminal CBYP (I/O, 4.5V to 120V domain). Multiplexed alternate functions: CBYP. Supported peripheral buses: General. |
| 2 | VOUT | Power_Out | Regulated power output rail (VOUT) operating in the 4.5V to 120V domain (Max rating: 120.0V). |
| 3 | ADJ | Digital_IO | Signal terminal ADJ (I/O, 4.5V to 120V domain). Multiplexed alternate functions: ADJ. Supported peripheral buses: General. |
| 4 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 5 | EN | Digital_IO | Chip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset. |
| 6 | NC | NC | Signal terminal NC (I/O, 4.5V to 120V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 7 | NC | NC | Signal terminal NC (I/O, 4.5V to 120V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 8 | VIN | Power_In | Primary positive power supply input (VIN) operating in the 4.5V to 120V domain (Max rating: 120.0V). |
| 9 | EXP | Digital_IO | Signal terminal EXP (I/O, 4.5V to 120V domain). Multiplexed alternate functions: EXP. Supported peripheral buses: General. |








