93LC76-I/P (PDIP-8) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of 93LC76-I/P (PDIP-8)?

Manufactured by MICROCHIP, the 93LC76-I/P is housed in a PDIP-8 package with 8 pins and a 2.54 mm lead pitch. Key pins include: 1 (CS: Multiplexed I/O & Peripheral Pin CS (General)), 2 (CLK: Multiplexed I/O & Peripheral Pin CLK (General)), 3 (DI: Multiplexed I/O & Peripheral Pin DI (General)), 4 (DO: Multiplexed I/O & Peripheral Pin DO (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (ORG: Multiplexed I/O & Peripheral Pin ORG (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for 93LC76-I/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), 93LC76-I/P (PDIP-8) has a nominal body envelope of 6.35 × 9.62 mm, pitch e = 2.54 mm, and 8 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for 93LC76-I/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for 93LC76-I/P (MICROCHIP, PDIP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 6.35mm × 9.62mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (8/8)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	CS	I/O	Multiplexed I/O & Peripheral Pin CS (General)
2	CLK	I/O	Multiplexed I/O & Peripheral Pin CLK (General)
3	DI	I/O	Multiplexed I/O & Peripheral Pin DI (General)
4	DO	I/O	Multiplexed I/O & Peripheral Pin DO (General)
5	VSS	GND	Ground Reference Pin (VSS)
6	ORG	I/O	Multiplexed I/O & Peripheral Pin ORG (General)
7	PE	I/O	Multiplexed I/O & Peripheral Pin PE (General)
8	VCC	Power	Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)

PIN 1 CS

I/O

Multiplexed I/O & Peripheral Pin CS (General)

Design note: Signal terminal CS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

93LC76-I/P (PDIP-8) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

93LC76-I/P (PDIP-8) - 2. Standard Pinout (Top View)

True package pinout (8 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

93LC76-I/P (PDIP-8) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

93LC76-I/P (PDIP-8) - 4. Package Dimensions (D×E×A)

PDIP-8 · 6.35×9.62mm · Pitch 2.54mmExpand ›

5. Recommended Land PatternLAND PATTERN

93LC76-I/P (PDIP-8) - 5. Recommended Land Pattern

IPC-7351B Footprint (8 Pads)Expand ›

6. Application SchematicSCHEMATIC

93LC76-I/P (PDIP-8) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)

Showing 1–10 of 10 uncropped original figures for 93LC76

P12 · p12_fig01EXACT PACKAGE

5.1 Package Marking Information

P1 · p01_fig011777×711px

P1 · p01_fig03873×1096px

 2010 Microchip Technology Inc. DS21131F-page 1

P12 · p12_fig02392×328px

Example

P12 · p12_fig04362×323px

Example | 93LC86 /SN0410 | 017 Example 93LC86 /SN0410 O® 017

P12 · p12_fig01P12

Datasheet Page 12 (p12_fig01)

P1 · p01_fig02All Packages in PDF

Block Diagram - Commercial (C) 0°C to +70°C - Industrial (I) -40°C to +85°C

P12 · p12_fig03All Packages in PDF

8-Lead SOIC (.150”) | XXXXXXXX XXXXYYWW | NNN

P14 · p14_fig01All Packages in PDF

93LC76-I/P (PDIP-8) — 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] - Note: _ For the most current package drawings, please see the Microchip Packaging Specification located at - http://www.microchip.com/packaging | DS21131F-page 14  2010 Micr

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] - Note: _ For the most current package drawings, please see the Microchip Packaging Specification located at - http://www.microchip.com/packaging | DS21131F-page 14  2010 Micr

P15 · p15_fig01All Packages in PDF

8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] - Note: _ For the most current package drawings, please see the Microchip Packaging Specification located at - http:/www.microchip.com/packaging |  2010 Microchip Technology I

Technical Specifications & Part Details (93LC76-I/P)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:93LC76-I/P (PDIP-8) is a 8-pin standard electronic & interconnect component featuring a 9.62 × 6.35 × 4.50 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 0°C to +70°C with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

0°C to +70°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

1 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

9.62 × 6.35 × 4.50 mm (A1=0.51 mm)

Package family: DIP (PDIP-8)

Pin Count & Lead PitchN / e

8 Pins | Pitch e = 2.54 mm (100.0 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol8 auto-grouped pins

IPC-7351B Land Pattern8 pads · Pitch 2.54mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-8)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

9.62 × 6.35 mm

Height (A) & Pitch (e)IPC-7351B

A=4.50mm · e=2.54mm

Pad Size (W × L)Level B

1.60 × 1.60 mm

Pins / Total PadsTopology

8P / 8Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit PDIP-8	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — 93LC76-I/P (PDIP-8)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of 93LC76-I/P (PDIP-8)?

Manufactured by MICROCHIP, the 93LC76-I/P is housed in a PDIP-8 package with 8 pins and a 2.54 mm lead pitch. Key pins include: 1 (CS: Multiplexed I/O & Peripheral Pin CS (General)), 2 (CLK: Multiplexed I/O & Peripheral Pin CLK (General)), 3 (DI: Multiplexed I/O & Peripheral Pin DI (General)), 4 (DO: Multiplexed I/O & Peripheral Pin DO (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (ORG: Multiplexed I/O & Peripheral Pin ORG (General)).

What are the IPC-7351B PCB Footprint dimensions for 93LC76-I/P?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), 93LC76-I/P (PDIP-8) has a nominal body envelope of 6.35 × 9.62 mm, pitch e = 2.54 mm, and 8 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for 93LC76-I/P?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for 93LC76-I/P (MICROCHIP, PDIP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (8 pins) & 93LC76 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	CS	Digital_IO	Signal terminal CS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS. Supported peripheral buses: General.
2	CLK	Digital_IO	Signal terminal CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLK. Supported peripheral buses: General.
3	DI	Digital_IO	Signal terminal DI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DI. Supported peripheral buses: General.
4	DO	Digital_IO	Signal terminal DO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DO. Supported peripheral buses: General.
5	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6	ORG	Digital_IO	Signal terminal ORG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ORG. Supported peripheral buses: General.
7	PE	Digital_IO	Signal terminal PE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE. Supported peripheral buses: General.
8	VCC	Power_In	Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).

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