24LC025-E/MC (TDFN-8-EP(2x3)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of 24LC025-E/MC (TDFN-8-EP(2x3))?

Manufactured by MICROCHIP, the 24LC025-E/MC is housed in a TDFN-8-EP(2x3) package with 9 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.7V to 5.5V. Key pins include: 1 (A0: Multiplexed I/O & Peripheral Pin A0 (General)), 2 (A1: Multiplexed I/O & Peripheral Pin A1 (General)), 3 (A2: Multiplexed I/O & Peripheral Pin A2 (General)), 4 (VSS: Ground Reference Pin (VSS)), 5 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)), 6 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)).

Q: What are the IPC-7351B PCB Footprint dimensions for 24LC025-E/MC?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), 24LC025-E/MC (TDFN-8-EP(2x3)) has a nominal body envelope of 2.00 × 3.00 mm, pitch e = 0.50 mm, and 9 copper pads plus a central exposed thermal pad (EPAD) of 1.50 × 1.50 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for 24LC025-E/MC?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for 24LC025-E/MC (MICROCHIP, TDFN-8-EP(2x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 2.00mm × 3.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (9/9)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	A0	I/O	Multiplexed I/O & Peripheral Pin A0 (General)
2	A1	I/O	Multiplexed I/O & Peripheral Pin A1 (General)
3	A2	I/O	Multiplexed I/O & Peripheral Pin A2 (General)
4	VSS	GND	Ground Reference Pin (VSS)
5	SDA	I/O	Multiplexed I/O & Peripheral Pin SDA (I2C)
6	SCL	I/O	Multiplexed I/O & Peripheral Pin SCL (I2C)
7	WP	I/O	Multiplexed I/O & Peripheral Pin WP (General)
8	VCC	Power	Power Supply Input (VCC — 1.7V to 5.5V)
9	GND	GND	Ground Reference Pin (GND)

PIN 1 A0

I/O

Multiplexed I/O & Peripheral Pin A0 (General)

Design note: AddressPinAO

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

24LC025-E/MC (TDFN-8-EP(2x3)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

24LC025-E/MC (TDFN-8-EP(2x3)) - 2. Standard Pinout (Top View)

True package pinout (9 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

24LC025-E/MC (TDFN-8-EP(2x3)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

24LC025-E/MC (TDFN-8-EP(2x3)) - 4. Package Dimensions (D×E×A)

TDFN-8-EP(2x3) · 2.00×3.00mm · Pitch 0.50mmExpand ›

5. Recommended Land PatternLAND PATTERN

24LC025-E/MC (TDFN-8-EP(2x3)) - 5. Recommended Land Pattern

IPC-7351B Footprint (9 Pads)Expand ›

6. Application SchematicSCHEMATIC

24LC025-E/MC (TDFN-8-EP(2x3)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)

Showing 1–8 of 8 uncropped original figures for 24LC025

P1 · p01_fig011779×663px

24AA025 1.7V-5.5V 400 kHz(1) I No

P1 · p01_fig021780×872px

PDIP/SOIC/TSSOP/MSOP

P1 · p01_fig03867×1048px

SDA SCL

P1 · p01_fig041777×821px

Note: WP pin is not internally connected on the 24XX025.

P1 · p01_fig02P1

Datasheet Page 1 (p01_fig02)

P12 · p12_fig011777×2564px

24AA024/24LC024/24AA025/24LC025

P12 · p12_fig01P12

Datasheet Page 12 (p12_fig01)

P23 · p23_fig01All Packages in PDF

24LC025-E/MC (TDFN-8-EP(2x3)) — 24AA024/24LC024/24AA025/24LC025 - 6-Lead Plastic Small Outline Transistor (OT) [SOT-23] - http:/Avww.microchip.com/packaging | © 2009 Microchip Technology Inc. DS21210N-page 23 | 3dêÜènóÜ§•îéqûÜóóm¶•óîüêr£Üü§î§•†£mrÄqmr/Ç | f†•ê§

24AA024/24LC024/24AA025/24LC025 - 6-Lead Plastic Small Outline Transistor (OT) [SOT-23] - http:/Avww.microchip.com/packaging | © 2009 Microchip Technology Inc. DS21210N-page 23 | 3dêÜènóÜ§•îéqûÜóóm¶•óîüêr£Üü§î§•†£mrÄqmr/Ç | f†•ê§

Technical Specifications & Part Details (24LC025-E/MC)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:24LC025-E/MC (TDFN-8-EP(2x3)) is a 8-pin standard electronic & interconnect component featuring a 3.00 × 2.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.7V to 5.5V supply operation across -40°C to +85°C with integrated I2C interfaces.

Operating Supply VoltageV_CC / V_DD

1.7V to 5.5V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

100 kHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

3.00 × 2.00 × 0.85 mm (A1=0.03 mm)

Package family: DFN (TDFN-8-EP(2x3))

Pin Count & Lead PitchN / e

8 Pins | Pitch e = 0.50 mm (19.7 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

I2C

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol9 auto-grouped pins

IPC-7351B Land Pattern9 pads · Pitch 0.50mm

IPC-7525 60% Solder PasteEPAD 1.50×1.50mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TDFN-8-EP(2x3))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

3.00 × 2.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.85mm · e=0.50mm

Pad Size (W × L)Level B

0.30 × 0.75 mm

Pins / Total PadsTopology

9P / 9Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit TDFN-8-EP(2x3)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — 24LC025-E/MC (TDFN-8-EP(2x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of 24LC025-E/MC (TDFN-8-EP(2x3))?

Manufactured by MICROCHIP, the 24LC025-E/MC is housed in a TDFN-8-EP(2x3) package with 9 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.7V to 5.5V. Key pins include: 1 (A0: Multiplexed I/O & Peripheral Pin A0 (General)), 2 (A1: Multiplexed I/O & Peripheral Pin A1 (General)), 3 (A2: Multiplexed I/O & Peripheral Pin A2 (General)), 4 (VSS: Ground Reference Pin (VSS)), 5 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)), 6 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)).

What are the IPC-7351B PCB Footprint dimensions for 24LC025-E/MC?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), 24LC025-E/MC (TDFN-8-EP(2x3)) has a nominal body envelope of 2.00 × 3.00 mm, pitch e = 0.50 mm, and 9 copper pads plus a central exposed thermal pad (EPAD) of 1.50 × 1.50 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for 24LC025-E/MC?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for 24LC025-E/MC (MICROCHIP, TDFN-8-EP(2x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (9 pins) & 24LC025 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	A0	Digital_IO	Signal terminal A0 (I/O, 1.7V to 5.5V domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
2	A1	Digital_IO	Signal terminal A1 (I/O, 1.7V to 5.5V domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
3	A2	Digital_IO	Signal terminal A2 (I/O, 1.7V to 5.5V domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
4	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
5	SDA	Digital_IO	Signal terminal SDA (I/O, 1.7V to 5.5V domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
6	SCL	Digital_IO	Signal terminal SCL (I/O, 1.7V to 5.5V domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
7	WP	Digital_IO	Signal terminal WP (I/O, 1.7V to 5.5V domain). Multiplexed alternate functions: WP. Supported peripheral buses: General.
8	VCC	Power_In	Primary positive power supply input (VCC) operating in the 1.7V to 5.5V domain (Max rating: 5.5V).
9	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.

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