AT28HC256-12JU (PLCC-32(11.4x14)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of AT28HC256-12JU (PLCC-32(11.4x14))?

Manufactured by MICROCHIP, the AT28HC256-12JU is housed in a PLCC-32(11.4x14) package with 32 pins and a 1.27 mm lead pitch. Key pins include: 1 (DC: Multiplexed I/O & Peripheral Pin DC (General)), 2 (A14: Multiplexed I/O & Peripheral Pin A14 (General)), 3 (A12: Multiplexed I/O & Peripheral Pin A12 (General)), 4 (A7: Multiplexed I/O & Peripheral Pin A7 (General)), 5 (A6: Multiplexed I/O & Peripheral Pin A6 (General)), 6 (A5: Multiplexed I/O & Peripheral Pin A5 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for AT28HC256-12JU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT28HC256-12JU (PLCC-32(11.4x14)) has a nominal body envelope of 11.40 × 14.00 mm, pitch e = 1.27 mm, and 32 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT28HC256-12JU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT28HC256-12JU (MICROCHIP, PLCC-32(11.4x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 11.40mm × 14.00mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (32/32)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	DC	I/O	Multiplexed I/O & Peripheral Pin DC (General)
2	A14	I/O	Multiplexed I/O & Peripheral Pin A14 (General)
3	A12	I/O	Multiplexed I/O & Peripheral Pin A12 (General)
4	A7	I/O	Multiplexed I/O & Peripheral Pin A7 (General)
5	A6	I/O	Multiplexed I/O & Peripheral Pin A6 (General)
6	A5	I/O	Multiplexed I/O & Peripheral Pin A5 (General)
7	A4	I/O	Multiplexed I/O & Peripheral Pin A4 (General)
8	A3	I/O	Multiplexed I/O & Peripheral Pin A3 (General)
9	A2	I/O	Multiplexed I/O & Peripheral Pin A2 (General)
10	A1	I/O	Multiplexed I/O & Peripheral Pin A1 (General)
11	A0	I/O	Multiplexed I/O & Peripheral Pin A0 (General)
12	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
13	I/O0	I/O	Multiplexed I/O & Peripheral Pin I/O0 (General)
14	I/O1	I/O	Multiplexed I/O & Peripheral Pin I/O1 (General)
15	I/O2	I/O	Multiplexed I/O & Peripheral Pin I/O2 (General)
16	GND	GND	Ground Reference Pin (GND)
17	DC	I/O	Multiplexed I/O & Peripheral Pin DC (General)
18	I/O3	I/O	Multiplexed I/O & Peripheral Pin I/O3 (General)
19	I/O4	I/O	Multiplexed I/O & Peripheral Pin I/O4 (General)
20	I/O5	I/O	Multiplexed I/O & Peripheral Pin I/O5 (General)
21	I/O6	I/O	Multiplexed I/O & Peripheral Pin I/O6 (General)
22	I/O7	I/O	Multiplexed I/O & Peripheral Pin I/O7 (General)
23	CE#	I/O	Multiplexed I/O & Peripheral Pin CE# (General)
24	A10	I/O	Multiplexed I/O & Peripheral Pin A10 (General)
25	OE#	I/O	Multiplexed I/O & Peripheral Pin OE# (General)
26	NC	I/O	Multiplexed I/O & Peripheral Pin NC (General)
27	A11	I/O	Multiplexed I/O & Peripheral Pin A11 (General)
28	A9	I/O	Multiplexed I/O & Peripheral Pin A9 (General)
29	A8	I/O	Multiplexed I/O & Peripheral Pin A8 (General)
30	A13	I/O	Multiplexed I/O & Peripheral Pin A13 (General)
31	WE#	I/O	Multiplexed I/O & Peripheral Pin WE# (General)
32	VCC	Power	Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)

PIN 1 DC

I/O

Multiplexed I/O & Peripheral Pin DC (General)

Design note: Signal terminal DC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DC. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

AT28HC256-12JU (PLCC-32(11.4x14)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

AT28HC256-12JU (PLCC-32(11.4x14)) - 2. Standard Pinout (Top View)

True package pinout (32 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

AT28HC256-12JU (PLCC-32(11.4x14)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

AT28HC256-12JU (PLCC-32(11.4x14)) - 4. Package Dimensions (D×E×A)

PLCC-32(11.4x14) · 11.40×14.00mm · Pitch 1.27mmExpand ›

5. Recommended Land PatternLAND PATTERN

AT28HC256-12JU (PLCC-32(11.4x14)) - 5. Recommended Land Pattern

IPC-7351B Footprint (32 Pads)Expand ›

6. Application SchematicSCHEMATIC

AT28HC256-12JU (PLCC-32(11.4x14)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)

Showing 1–7 of 7 uncropped original figures for AT28HC256

P1 · p01_fig01456×280px

Military Grade 256-Kbit (32,768 x 8) High-Speed

P5 · p05_fig011775×1775px

2. Pin Descriptions

P21 · p21_fig011913×2125px

7. Packaging Information

P24 · p24_fig011779×2090px

AT28HC256-12JU (PLCC-32(11.4x14)) — TITLE DRAWING NO. REV. 32L, 32-pad, Non-windowed, Ceramic Lid, Leadless Chip Carrier (LCC) B 32L | 10/21/03 | Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 C-12 | 11.63(0.458) 11.23(0.442) | 14.22(0.560

TITLE DRAWING NO. REV. 32L, 32-pad, Non-windowed, Ceramic Lid, Leadless Chip Carrier (LCC) B 32L | 10/21/03 | Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 C-12 | 11.63(0.458) 11.23(0.442) | 14.22(0.560

P24 · p24_fig01P24

Datasheet Page 24 (p24_fig01)

P22 · p22_fig01All Packages in PDF

AT28HC256-12JU (PLCC-32(11.4x14)) — TITLE DRAWING NO. REV. 28D6, 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) B 28D6 | 10/23/03 | 37.85(1.490) 36.58(1.440) PIN | 1 | 15.49(0.610) 12.95(0.510) | 0.127(0.005)MIN | 1.52(0.060) 0.38(0.015) 0.66(0.026)

TITLE DRAWING NO. REV. 28D6, 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) B 28D6 | 10/23/03 | 37.85(1.490) 36.58(1.440) PIN | 1 | 15.49(0.610) 12.95(0.510) | 0.127(0.005)MIN | 1.52(0.060) 0.38(0.015) 0.66(0.026)

P25 · p25_fig01EXACT PACKAGE

PACKAGE_DIMENSIONS — AT28HC256-90TU-T (TSOP-28-10.1mm)

Technical Specifications & Part Details (AT28HC256-12JU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:AT28HC256-12JU (PLCC-32(11.4x14)) is a 32-pin standard electronic & interconnect component featuring a 14.00 × 11.40 × 1.15 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -55°C to +125°C with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-55°C to +125°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

5 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

14.00 × 11.40 × 1.15 mm (A1=0.03 mm)

Package family: LGA (PLCC-32(11.4x14))

Pin Count & Lead PitchN / e

32 Pins | Pitch e = 1.27 mm (50.0 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol32 auto-grouped pins

IPC-7351B Land Pattern32 pads · Pitch 1.27mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

IPC-7351B

Family Variants & Same Datasheet Chips — AT28HC256 (2)

Select package variant or sibling MPN sharing this datasheet

TSOP-28-10.1mm · 28P

AT28HC256-90TU-T

MICROCHIP·TSOP-28-10.1mm

IPC-7351B

28P18.3×10.1×2.50mmP=1.27mm

AT28HC256 (TSOP-28-10.1mm)

PLCC-32(11.4x14) · 32P

AT28HC256-12JU

MICROCHIP·PLCC-32(11.4x14)

IPC-7351B

32P14.0×11.4×1.15mmP=1.27mm

AT28HC256 (PLCC-32(11.4x14))

Mechanical Dimensions & Land Pattern (PLCC-32(11.4x14))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

14.00 × 11.40 mm

Height (A) & Pitch (e)IPC-7351B

A=1.15mm · e=1.27mm

Pad Size (W × L)Level B

0.62 × 2.40 mm

Pins / Total PadsTopology

32P / 32Pad (LGA_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit PLCC-32(11.4x14)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT28HC256-12JU (PLCC-32(11.4x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT28HC256-12JU (PLCC-32(11.4x14))?

Manufactured by MICROCHIP, the AT28HC256-12JU is housed in a PLCC-32(11.4x14) package with 32 pins and a 1.27 mm lead pitch. Key pins include: 1 (DC: Multiplexed I/O & Peripheral Pin DC (General)), 2 (A14: Multiplexed I/O & Peripheral Pin A14 (General)), 3 (A12: Multiplexed I/O & Peripheral Pin A12 (General)), 4 (A7: Multiplexed I/O & Peripheral Pin A7 (General)), 5 (A6: Multiplexed I/O & Peripheral Pin A6 (General)), 6 (A5: Multiplexed I/O & Peripheral Pin A5 (General)).

What are the IPC-7351B PCB Footprint dimensions for AT28HC256-12JU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT28HC256-12JU (PLCC-32(11.4x14)) has a nominal body envelope of 11.40 × 14.00 mm, pitch e = 1.27 mm, and 32 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT28HC256-12JU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT28HC256-12JU (MICROCHIP, PLCC-32(11.4x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (32 pins) & AT28HC256 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	DC	Digital_IO	Signal terminal DC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DC. Supported peripheral buses: General.
2	A14	Digital_IO	Signal terminal A14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A14. Supported peripheral buses: General.
3	A12	Digital_IO	Signal terminal A12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A12. Supported peripheral buses: General.
4	A7	Digital_IO	Signal terminal A7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A7. Supported peripheral buses: General.
5	A6	Digital_IO	Signal terminal A6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6. Supported peripheral buses: General.
6	A5	Digital_IO	Signal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
7	A4	Digital_IO	Signal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
8	A3	Digital_IO	Signal terminal A3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A3. Supported peripheral buses: General.
9	A2	Digital_IO	Signal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
10	A1	Digital_IO	Signal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
11	A0	Digital_IO	Signal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
12	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13	I/O0	Digital_IO	Signal terminal I/O0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O0. Supported peripheral buses: General.
14	I/O1	Digital_IO	Signal terminal I/O1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O1. Supported peripheral buses: General.
15	I/O2	Digital_IO	Signal terminal I/O2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O2. Supported peripheral buses: General.
16	GND	GND	0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
17	DC	Digital_IO	Signal terminal DC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DC. Supported peripheral buses: General.
18	I/O3	Digital_IO	Signal terminal I/O3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O3. Supported peripheral buses: General.
19	I/O4	Digital_IO	Signal terminal I/O4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O4. Supported peripheral buses: General.
20	I/O5	Digital_IO	Signal terminal I/O5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O5. Supported peripheral buses: General.
21	I/O6	Digital_IO	Signal terminal I/O6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O6. Supported peripheral buses: General.
22	I/O7	Digital_IO	Signal terminal I/O7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I/O7. Supported peripheral buses: General.
23	CE#	Digital_IO	Signal terminal CE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CE#. Supported peripheral buses: General.
24	A10	Digital_IO	Signal terminal A10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A10. Supported peripheral buses: General.
25	OE#	Digital_IO	Signal terminal OE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OE#. Supported peripheral buses: General.
26	NC	NC	Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
27	A11	Digital_IO	Signal terminal A11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A11. Supported peripheral buses: General.
28	A9	Digital_IO	Signal terminal A9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A9. Supported peripheral buses: General.
29	A8	Digital_IO	Signal terminal A8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A8. Supported peripheral buses: General.
30	A13	Digital_IO	Signal terminal A13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A13. Supported peripheral buses: General.
31	WE#	Digital_IO	Signal terminal WE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WE#. Supported peripheral buses: General.
32	VCC	Power_In	Primary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).

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