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STM32L471ZGJ6 (UFBGA-144) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L471ZGJ6

STID: C1345561UFBGA-144 · 144 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L471ZGJ6 (UFBGA-144)A1VSSA2PE0A3PB8A4BOOT0A5PB7A6PG14A7PG12A8PD7A9PD6A10PD1A11PD0A12VSSB1VBATB2PE4B3PE3B4PE1B5PB6B6PG15B7PG11B8PD5B9PC12B10PC10B11PA12B12PA11C1IOC1C2PE5C3PE2C4PB9C5PB5C6PB3 (JTDO - C7PG9C8PD4C9PC11C10PA14 (JTCKSWC11PA13 (JTMSSWC12PA10D1PF4D2PC14 - OSC32D3PE6D4PC13D5PB4 (NJTRST)D6PG13D7PG10D8PD3D9PD2D10PA15(JTDI)D11PA9D12PA8E1PF6E2PF1E3PF0E4PF2E5VSSE6VDDIO2E7VDDE8VSSE9VDDE10PC6E11PC9E12PC8F1PF8F2PF7F3PF5F4PF3F5VDDF6VSSF7VSSF8VDDIO2F9PG7F10PG6F11PG8F12PC7M12VSSM11PE15M10PE10M9PF15M8PE7M7PF14M6PB1M5PC5M4PA7M3PA5M2PA3M1VSSL12PB15L11PB10L10PE14L9PE13L8PE12L7PE8L6PF13L5PB0L4OPAMP2_VINML3PA4L2PA2L1OPAMP1_VINMK12PD9K11PD8K10PB12K9PB11K8PE11K7PG0K6PF12K5PB2K4PA6K3PA1K2VDDAK1VREF+J12PD15J11PD10J10PB14J9PB13J8PE9J7PG1J6PF11J5PC4J4PC3J3PA0J2VREF -J1VSSAH12PG2H11PD14H10PD11H9PD12H8VSSH7VDDH6VDDH5VSSH4NRSTH3PC1H2PC0H1PC2G12PG5G11PG3G10PD13G9PG4G8VDDG7VSSG6VSSG5VDDG4PF9G3PF10G2PH0OSC IN -_G1PH1OSC OUT -Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.896.591.486.481.376.271.166.061.055.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9-61.0-66.0-71.1-76.2-81.3-86.4-91.4-96.5mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1L1M1A2B2C2D2E2F2G2H2J2K2L2M2A3B3C3D3E3F3G3H3J3K3L3M3A4B4C4D4E4F4G4H4J4K4L4M4A5B5C5D5E5F5G5H5J5K5L5M5A6B6C6D6E6F6G6H6J6K6L6M6A7B7C7D7E7F7G7H7J7K7L7M7A8B8C8D8E8F8G8H8J8K8L8M8A9B9C9D9E9F9G9H9J9K9L9M9A10B10C10D10E10F10G10H10J10K10L10M10A11B11C11D11E11F11G11H11J11K11L11M11A12B12C12D12E12F12G12H12J12K12L12M12E=10.00mm · Pitch e=0.80mmD=10.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (144/144)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VSSGNDGround Reference Pin (VSS)
A2PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
A3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (PWM, CAN)
A4BOOT0IInput-Only Pin BOOT0 (General)
A5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART)
A6PG14I/OMultiplexed I/O & Peripheral Pin PG14 (I2C)
A7PG12I/OMultiplexed I/O & Peripheral Pin PG12 (UART)
A8PD7I/OMultiplexed I/O & Peripheral Pin PD7 (UART)
A9PD6I/OMultiplexed I/O & Peripheral Pin PD6 (UART)
A10PD1I/OMultiplexed I/O & Peripheral Pin PD1 (SPI, CAN)
A11PD0I/OMultiplexed I/O & Peripheral Pin PD0 (SPI, CAN)
A12VSSGNDGround Reference Pin (VSS)
B1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B2PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
B3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
B4PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART)
B6PG15I/OMultiplexed I/O & Peripheral Pin PG15 (I2C)
B7PG11I/OMultiplexed I/O & Peripheral Pin PG11 (UART)
B8PD5I/OMultiplexed I/O & Peripheral Pin PD5 (UART)
B9PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
B10PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
B11PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, CAN)
B12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, PWM)
C1IOC1I/OGeneral Purpose Digital I/O Pin IOC1
C2PE5I/OMultiplexed I/O & Peripheral Pin PE5 (SPI)
C3PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
C4PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C, CAN)
C5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C)
C6PB3 (JTDO - TRACESWO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO - TRACESWO) (UART, SPI, PWM, SWD/JTAG)
C7PG9I/OMultiplexed I/O & Peripheral Pin PG9 (SPI)
C8PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART, SPI)
C9PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
C10PA14 (JTCKSWCLK) -I/OMultiplexed I/O & Peripheral Pin PA14 (JTCKSWCLK) - (SWD/JTAG)
C11PA13 (JTMSSWDIO) -I/OMultiplexed I/O & Peripheral Pin PA13 (JTMSSWDIO) - (SWD/JTAG)
C12PA10I/OMultiplexed I/O & Peripheral Pin PA10 (PWM)
D1PF4I/OMultiplexed I/O & Peripheral Pin PF4 (ADC)
D2PC14 - OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (PC14) (RTC/CLK)
D3PE6I/OMultiplexed I/O & Peripheral Pin PE6 (RTC/CLK)
D4PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
D5PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (UART, SPI, SWD/JTAG)
D6PG13I/OMultiplexed I/O & Peripheral Pin PG13 (I2C)
D7PG10I/OMultiplexed I/O & Peripheral Pin PG10 (UART)
D8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, SPI)
D9PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
D10PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)
D11PA9I/OMultiplexed I/O & Peripheral Pin PA9 (PWM)
D12PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
E1PF6I/OMultiplexed I/O & Peripheral Pin PF6 (ADC)
E2PF1I/OMultiplexed I/O & Peripheral Pin PF1 (I2C)
E3PF0I/OMultiplexed I/O & Peripheral Pin PF0 (I2C)
E4PF2I/OMultiplexed I/O & Peripheral Pin PF2 (I2C)
E5VSSGNDGround Reference Pin (VSS)
E6VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
E7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E8VSSGNDGround Reference Pin (VSS)
E9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E10PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
E11PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E12PC8I/OMultiplexed I/O & Peripheral Pin PC8 (PWM)
F1PF8I/OMultiplexed I/O & Peripheral Pin PF8 (ADC)
F2PF7I/OMultiplexed I/O & Peripheral Pin PF7 (ADC, PWM)
F3PF5I/OMultiplexed I/O & Peripheral Pin PF5 (ADC)
F4PF3I/OMultiplexed I/O & Peripheral Pin PF3 (ADC)
F5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F6VSSGNDGround Reference Pin (VSS)
F7VSSGNDGround Reference Pin (VSS)
F8VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
F9PG7I/OMultiplexed I/O & Peripheral Pin PG7 (I2C)
F10PG6I/OMultiplexed I/O & Peripheral Pin PG6 (UART, I2C)
F11PG8I/OMultiplexed I/O & Peripheral Pin PG8 (I2C)
F12PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
G1PH1OSC OUT -_ (PH1)I/OMultiplexed I/O & Peripheral Pin PH1OSC OUT -_ (PH1) (RTC/CLK)
G2PH0OSC IN -_ (PH0)I/OMultiplexed I/O & Peripheral Pin PH0OSC IN -_ (PH0) (RTC/CLK)
G3PF10I/OMultiplexed I/O & Peripheral Pin PF10 (ADC)
G4PF9I/OMultiplexed I/O & Peripheral Pin PF9 (ADC)
G5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G6VSSGNDGround Reference Pin (VSS)
G7VSSGNDGround Reference Pin (VSS)
G8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G9PG4I/OMultiplexed I/O & Peripheral Pin PG4 (SPI)
G10PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
G11PG3I/OMultiplexed I/O & Peripheral Pin PG3 (SPI)
G12PG5I/OMultiplexed I/O & Peripheral Pin PG5 (UART, SPI)
H1PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
H2PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
H3PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
H4NRSTISystem Enable & Hardware Reset (NRST)
H5VSSGNDGround Reference Pin (VSS)
H6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H8VSSGNDGround Reference Pin (VSS)
H9PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART, PWM)
H10PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART, I2C)
H11PD14I/OMultiplexed I/O & Peripheral Pin PD14 (PWM)
H12PG2I/OMultiplexed I/O & Peripheral Pin PG2 (SPI)
J1VSSAGNDGround Reference Pin (VSSA)
J2VREF -AnalogMultiplexed I/O & Peripheral Pin VREF - (General)
J3PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
J4PC3I/OMultiplexed I/O & Peripheral Pin PC3 (I2C, ADC)
J5PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
J6PF11I/OMultiplexed I/O & Peripheral Pin PF11 (General)
J7PG1I/OMultiplexed I/O & Peripheral Pin PG1 (General)
J8PE9I/OMultiplexed I/O & Peripheral Pin PE9 (PWM)
J9PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
J10PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, I2C, PWM)
J11PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART, SPI)
J12PD15I/OMultiplexed I/O & Peripheral Pin PD15 (PWM)
K1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
K2VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
K3PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
K4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, ADC)
K5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
K6PF12I/OMultiplexed I/O & Peripheral Pin PF12 (General)
K7PG0I/OMultiplexed I/O & Peripheral Pin PG0 (General)
K8PE11I/OMultiplexed I/O & Peripheral Pin PE11 (PWM)
K9PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, PWM)
K10PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, I2C)
K11PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
K12PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
L1OPAMP1_VINMPowerPower Supply Input (OPAMP1_VINM — 3.3V VDD (Max 4.0V))
L2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
L3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
L4OPAMP2_VINMPowerPower Supply Input (OPAMP2_VINM — 3.3V VDD (Max 4.0V))
L5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM)
L6PF13I/OMultiplexed I/O & Peripheral Pin PF13 (General)
L7PE8I/OMultiplexed I/O & Peripheral Pin PE8 (PWM)
L8PE12I/OMultiplexed I/O & Peripheral Pin PE12 (PWM)
L9PE13I/OMultiplexed I/O & Peripheral Pin PE13 (PWM)
L10PE14I/OMultiplexed I/O & Peripheral Pin PE14 (SPI, PWM)
L11PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, PWM)
L12PB15I/OMultiplexed I/O & Peripheral Pin PB15 (PWM, RTC/CLK)
M1VSSGNDGround Reference Pin (VSS)
M2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
M3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (ADC, DAC, PWM)
M4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (ADC, PWM)
M5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
M6PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
M7PF14I/OMultiplexed I/O & Peripheral Pin PF14 (General)
M8PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
M9PF15I/OMultiplexed I/O & Peripheral Pin PF15 (General)
M10PE10I/OMultiplexed I/O & Peripheral Pin PE10 (PWM)
M11PE15I/OMultiplexed I/O & Peripheral Pin PE15 (SPI)
M12VSSGNDGround Reference Pin (VSS)
PIN A1 VSS
GND
Ground Reference Pin (VSS)
Design note: 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 16 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L471ZGJ6 (ST · UFBGA-144)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L471ZGJ6 (UFBGA-144) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L471ZGJ6 (UFBGA-144) - 2. Standard Pinout (Top View)
True package pinout (144 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L471ZGJ6 (UFBGA-144) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L471ZGJ6 (UFBGA-144) - 4. Package Dimensions (D×E×A)
UFBGA-144 · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L471ZGJ6 (UFBGA-144) - 5. Recommended Land Pattern
IPC-7351B Footprint (144 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L471ZGJ6 (UFBGA-144) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (16 figures · Page 1/2)
Showing 1–12 of 16 uncropped original figures for STM32L471
P59 · p59_fig01EXACT PACKAGE
STM32L471ZGJ6 (UFBGA-144) — Figure 6. STM32L471Zx LQFP144 pinout(1) PG11 PG12 PG13 PG14 VSS VDDIO2 PG15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS VDD 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Figure 6. STM32L471Zx LQFP144 pinout(1) PG11 PG12 PG13 PG14 VSS VDDIO2 PG15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS VDD 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
P60 · p60_fig01EXACT PACKAGE
STM32L471ZGJ6 (UFBGA-144) — Figure 7. STM32L471Zx UFBGA144 ballout(1)
Figure 7. STM32L471Zx UFBGA144 ballout(1)
P209 · p209_fig01EXACT PACKAGE
STM32L471ZGJ6 (UFBGA-144) — Figure 51. LQFP - 144-pin,20 x 20 mm low-profile quad flat package
Figure 51. LQFP - 144-pin,20 x 20 mm low-profile quad flat package
P211 · p211_fig01EXACT PACKAGE
STM32L471ZGJ6 (UFBGA-144) — Figure 53. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
Figure 53. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
P212 · p212_fig01EXACT PACKAGE
STM32L471ZGJ6 (UFBGA-144) — Figure 54. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
Figure 54. UFBGA - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball
P1 · p01_fig011269×469px
STM32L471ZGJ6 (UFBGA-144) — • Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
• Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
P59 · p59_fig01P59
STM32L471ZGJ6 (UFBGA-144) — Datasheet Page 59 (p59_fig01)
Datasheet Page 59 (p59_fig01)
P60 · p60_fig021546×1255px
STM32L471ZGJ6 (UFBGA-144) — VREF+ VDDA PA1 PA6 PB2 PE11 PB11 PB12 PD8 PD9
VREF+ VDDA PA1 PA6 PB2 PE11 PB11 PB12 PD8 PD9
P60 · p60_fig01P60
STM32L471ZGJ6 (UFBGA-144) — Datasheet Page 60 (p60_fig01)
Datasheet Page 60 (p60_fig01)
P62 · p62_fig011711×906px
STM32L471ZGJ6 (UFBGA-144) — 62/229 DS10741 Rev 3
62/229 DS10741 Rev 3
P96 · p96_fig011751×1932px
STM32L471ZGJ6 (UFBGA-144) — Figure 14. Power supply scheme
Figure 14. Power supply scheme
P96 · p96_fig01P96
STM32L471ZGJ6 (UFBGA-144) — Datasheet Page 96 (p96_fig01)
Datasheet Page 96 (p96_fig01)
Page 1 / 2 (16 extracted figures)

Technical Specifications & Part Details (STM32L471ZGJ6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L471ZGJ6 (UFBGA-144) is a 144-pin embedded microcontroller unit (mcu) featuring a 10.00 × 10.00 × 0.53 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
80 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
106 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 0.53 mm (A1=0.20 mm)
Package family: BGA (UFBGA-144)
Pin Count & Lead PitchN / e
144 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol144 auto-grouped pins
OK
IPC-7351B Land Pattern144 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-144)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.53mm · e=0.80mm
Pad Size (W × L)Level B
0.32 × 0.32 mm
Pins / Total PadsTopology
144P / 144Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-144
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L471ZGJ6 (UFBGA-144)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L471ZGJ6 (UFBGA-144)?

Manufactured by ST, the STM32L471ZGJ6 is housed in a UFBGA-144 package with 144 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (VSS: Ground Reference Pin (VSS)), A2 (PE0: Multiplexed I/O & Peripheral Pin PE0 (General)), A3 (PB8: Multiplexed I/O & Peripheral Pin PB8 (PWM, CAN)), A4 (BOOT0: Input-Only Pin BOOT0 (General)), A5 (PB7: Multiplexed I/O & Peripheral Pin PB7 (UART)), A6 (PG14: Multiplexed I/O & Peripheral Pin PG14 (I2C)).

What are the IPC-7351B PCB Footprint dimensions for STM32L471ZGJ6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L471ZGJ6 (UFBGA-144) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 144 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L471ZGJ6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L471ZGJ6 (ST, UFBGA-144) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (144 pins) & STM32L471 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
A2PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
A3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: PWM, CAN.
A4BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART.
A6PG14Digital_IOSignal terminal PG14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG14. Supported peripheral buses: I2C.
A7PG12Digital_IOSignal terminal PG12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG12. Supported peripheral buses: UART.
A8PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: UART.
A9PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: UART.
A10PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI, CAN.
A11PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, CAN.
A12VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B2PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
B3PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
B4PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART.
B6PG15Digital_IOSignal terminal PG15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBAEVENTOUT. Supported peripheral buses: I2C.
B7PG11Digital_IOSignal terminal PG11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG11. Supported peripheral buses: UART.
B8PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: UART.
B9PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSIUSART3CK. Supported peripheral buses: UART, SPI.
B10PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCKUSART3TX. Supported peripheral buses: UART, SPI.
B11PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART, CAN.
B12PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART, PWM.
C1IOC1Digital_IOGeneral Purpose Digital I/O Pin IOC1
C2PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: SPI.
C3PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
C4PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: I2C, CAN.
C5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSIUSART1CK. Supported peripheral buses: UART, SPI, I2C.
C6PB3 (JTDO - TRACESWO)Digital_IOSignal terminal PB3 (JTDO - TRACESWO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI, PWM, SWD/JTAG.
C7PG9Digital_IOSignal terminal PG9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCKUSART1TX. Supported peripheral buses: SPI.
C8PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI.
C9PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISOUSART3RX. Supported peripheral buses: UART, SPI.
C10PA14 (JTCKSWCLK) -Digital_IOSignal terminal PA14 (JTCKSWCLK) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (JTCKSWCLK) -. Supported peripheral buses: SWD/JTAG.
C11PA13 (JTMSSWDIO) -Digital_IOSignal terminal PA13 (JTMSSWDIO) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMSSWDIO) -. Supported peripheral buses: SWD/JTAG.
C12PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: PWM.
D1PF4Digital_IOSignal terminal PF4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: ADC.
D2PC14 - OSC32_IN (PC14)Digital_IOSignal terminal PC14 - OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
D3PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: RTC/CLK.
D4PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
D5PB4 (NJTRST)Digital_IOSignal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOSPI3MISO. Supported peripheral buses: UART, SPI, SWD/JTAG.
D6PG13Digital_IOSignal terminal PG13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG13. Supported peripheral buses: I2C.
D7PG10Digital_IOSignal terminal PG10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG10. Supported peripheral buses: UART.
D8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI.
D9PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
D10PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
D11PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: PWM.
D12PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
E1PF6Digital_IOSignal terminal PF6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF6. Supported peripheral buses: ADC.
E2PF1Digital_IOSignal terminal PF1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: I2C.
E3PF0Digital_IOSignal terminal PF0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: I2C.
E4PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: I2C.
E5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E6VDDIO2Power_InPrimary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E10PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
E11PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E12PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: PWM.
F1PF8Digital_IOSignal terminal PF8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF8. Supported peripheral buses: ADC.
F2PF7Digital_IOSignal terminal PF7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF7. Supported peripheral buses: ADC, PWM.
F3PF5Digital_IOSignal terminal PF5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: ADC.
F4PF3Digital_IOSignal terminal PF3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: ADC.
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