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STM32L452VCI6 (UFBGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L452VCI6

STID: C1345395UFBGA-100 · 100 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L452VCI6 (UFBGA-100)A1PE3A2PE1A3PB8A4PH3 - BOOT0 A5PD7A6PD5A7PB4 (NJTRST)A8PB3 (JTDO/ TA9PA15 (JTDI)A10PA14 (JTCK/ A11PA13 (JTMS/ A12PA12B1PE4B2PE2B3PB9B4PB7B5PB6B6PD6B7PD4B8PD3B9PD1B10PC12B11PC10B12PA11C1PC13C2PE5C3PE0C4VDDC5PB5C8PD2C9PD0C10PC11C11VDDUSBC12PA10D1IOD1D2PE6D3VSSD10PA9D11PA8D12PC9E1IOE1E2VBATE3VSSE10PC8E11PC7E12PC6F1PH0 - OSC_INF2VSSF11VSSF12VSSM12PE15M11PE14M10PE13M9PE11M8PE9M7PE7M6PB1M5PB0M4PA7M3PA4M2PA1M1VDDAL12PB12L11PB11L10PB10L9PE12L8PE10L7PE8L6PB2L5PC5L4PA6L3PA3L2PA0L1VREF+K12PB13K11PB14K10PB15K9PD8K8PD9K5PC4K4PA5K3PA2K2PC3K1VREF -J12PD10J11PD11J10PD12J3PC2J2PC1J1VSSAH12PD13H11PD14H10PD15H3VDDH2NRSTH1PC0G12VDDG11VDDG2VDDG1PH1 - OSC_ OGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8A9A10A11A12B1B2B3B4B5B6B7B8B9B10B11B12C1C2C3C4C5C8C9C10C11C12D1D2D3D10D11D12E1E2E3E10E11E12F1F2F11F12G1G2G11G12H1H2H3H10H11H12J1J2J3J10J11J12K1K2K3K4K5K8K9K10K11K12L1L2L3L4L5L6L7L8L9L10L11L12M1M2M3M4M5M6M7M8M9M10M11M12E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
A2PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
A3PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C)
A4PH3 - BOOT0 (BOOT0)I/OMultiplexed I/O & Peripheral Pin PH3 - BOOT0 (BOOT0) (General)
A5PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
A6PD5I/OMultiplexed I/O & Peripheral Pin PD5 (UART)
A7PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (UART, SPI, I2C, SWD/JTAG)
A8PB3 (JTDO/ TRACE SWO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO/ TRACE SWO) (UART, SPI, SWD/JTAG)
A9PA15 (JTDI)I/OMultiplexed I/O & Peripheral Pin PA15 (JTDI) (UART, SPI, SWD/JTAG)
A10PA14 (JTCK/ SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK/ SWCLK) (I2C, SWD/JTAG)
A11PA13 (JTMS/ SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13 (JTMS/ SWDIO) (USB, SWD/JTAG)
A12PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART)
B1PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
B2PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
B3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (I2C, CAN)
B4PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
B6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
B7PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART, SPI)
B8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, SPI)
B9PD1I/OMultiplexed I/O & Peripheral Pin PD1 (SPI, CAN)
B10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
B11PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
B12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI, PWM)
C1PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
C2PE5I/OMultiplexed I/O & Peripheral Pin PE5 (SPI)
C3PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
C4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
C5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, CAN)
C8PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
C9PD0I/OMultiplexed I/O & Peripheral Pin PD0 (SPI, CAN)
C10PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
C11VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
C12PA10I/OMultiplexed I/O & Peripheral Pin PA10 (USB, UART, I2C, PWM)
D1IOD1I/OGeneral Purpose Digital I/O Pin IOD1
D2PE6I/OMultiplexed I/O & Peripheral Pin PE6 (RTC/CLK)
D3VSSGNDGround Reference Pin (VSS)
D10PA9I/OMultiplexed I/O & Peripheral Pin PA9 (PWM)
D11PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
D12PC9I/OMultiplexed I/O & Peripheral Pin PC9 (USB)
E1IOE1I/OGeneral Purpose Digital I/O Pin IOE1
E2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
E3VSSGNDGround Reference Pin (VSS)
E10PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
E11PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
E12PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
F1PH0 - OSC_IN (PH0)I/OMultiplexed I/O & Peripheral Pin PH0 - OSC_IN (PH0) (RTC/CLK)
F2VSSGNDGround Reference Pin (VSS)
F11VSSGNDGround Reference Pin (VSS)
F12VSSGNDGround Reference Pin (VSS)
G1PH1 - OSC_ OUT (PH1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC_ OUT (PH1) (RTC/CLK)
G2VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G11VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G12VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (I2C, ADC)
H2NRSTISystem Enable & Hardware Reset (NRST)
H3VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H10PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
H11PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
H12PD13I/OMultiplexed I/O & Peripheral Pin PD13 (I2C)
J1VSSAGNDGround Reference Pin (VSSA)
J2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (I2C, ADC)
J3PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
J10PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART, I2C)
J11PD11I/OMultiplexed I/O & Peripheral Pin PD11 (I2C)
J12PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART)
K1VREF -AnalogMultiplexed I/O & Peripheral Pin VREF - (General)
K2PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
K3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (PWM)
K4PA5I/OMultiplexed I/O & Peripheral Pin PA5 (ADC)
K5PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART)
K8PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
K9PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
K10PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, RTC/CLK)
K11PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
K12PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
L1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
L2PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
L3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (ADC, PWM)
L4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
L5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
L6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
L7PE8I/OMultiplexed I/O & Peripheral Pin PE8 (SPI, PWM)
L8PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
L9PE12I/OMultiplexed I/O & Peripheral Pin PE12 (PWM)
L10PB10I/OMultiplexed I/O & Peripheral Pin PB10 (SPI, I2C)
L11PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
L12PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, I2C, CAN)
M1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
M2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, ADC, PWM)
M3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
M4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (I2C, ADC, PWM)
M5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM)
M6PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, PWM)
M7PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
M8PE9I/OMultiplexed I/O & Peripheral Pin PE9 (PWM)
M9PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
M10PE13I/OMultiplexed I/O & Peripheral Pin PE13 (PWM)
M11PE14I/OMultiplexed I/O & Peripheral Pin PE14 (PWM)
M12PE15I/OMultiplexed I/O & Peripheral Pin PE15 (SPI)
PIN A1 PE3
I/O
Multiplexed I/O & Peripheral Pin PE3 (General)
Design note: Alt: TRACED0 TIM3 CH1 ,_ , TSC G7 IO2_SAI1SDB_ ,__ , EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L452VCI6 (ST · UFBGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L452VCI6 (UFBGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L452VCI6 (UFBGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L452VCI6 (UFBGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L452VCI6 (UFBGA-100) - 4. Package Dimensions (D×E×A)
UFBGA-100 · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L452VCI6 (UFBGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L452VCI6 (UFBGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for STM32L452
P57 · p57_fig01EXACT PACKAGE
STM32L452VCI6 (UFBGA-100) — Figure 6. STM32L452Vx LQFP100 pinout(1)
Figure 6. STM32L452Vx LQFP100 pinout(1)
P58 · p58_fig01EXACT PACKAGE
STM32L452VCI6 (UFBGA-100) — Figure 7. STM32L452Vx UFBGA100 ballout(1)
Figure 7. STM32L452Vx UFBGA100 ballout(1)
P196 · p196_fig01EXACT PACKAGE
STM32L452VCI6 (UFBGA-100) — Figure 46. UFBGA100 -Outline
Figure 46. UFBGA100 -Outline
P197 · p197_fig01EXACT PACKAGE
STM32L452VCI6 (UFBGA-100) — Figure 47. UFBGA100 - Recommended footprint
Figure 47. UFBGA100 - Recommended footprint
P1 · p01_fig01881×475px
STM32L452VCI6 (UFBGA-100) — • RTC with HW calendar, alarms and calibration
• RTC with HW calendar, alarms and calibration
P58 · p58_fig01P58
STM32L452VCI6 (UFBGA-100) — Datasheet Page 58 (p58_fig01)
Datasheet Page 58 (p58_fig01)
P93 · p93_fig011546×1275px
STM32L452VCI6 (UFBGA-100) — Figure 18. Power supply scheme
Figure 18. Power supply scheme
P93 · p93_fig01P93
STM32L452VCI6 (UFBGA-100) — Datasheet Page 93 (p93_fig01)
Datasheet Page 93 (p93_fig01)
P133 · p133_fig011546×702px
STM32L452VCI6 (UFBGA-100) — Figure 23. Typical application with an 8 MHz crystal
Figure 23. Typical application with an 8 MHz crystal
P134 · p134_fig011546×702px
STM32L452VCI6 (UFBGA-100) — Figure 24. Typical application with a 32.768 kHz crystal
Figure 24. Typical application with a 32.768 kHz crystal
P203 · p203_fig011546×1432px
STM32L452VCI6 (UFBGA-100) — Figure 53. UFBGA64 - Recommended footprint
Figure 53. UFBGA64 - Recommended footprint
P206 · p206_fig011546×810px
STM32L452VCI6 (UFBGA-100) — Figure 56. WLCSP64 - Recommended footprint
Figure 56. WLCSP64 - Recommended footprint
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (STM32L452VCI6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L452VCI6 (UFBGA-100) is a 100-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
80 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
80 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.60 mm (A1=0.20 mm)
Package family: BGA (UFBGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, CAN, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3 - BOOT0 (BOOT0)): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.28 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-100
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L452VCI6 (UFBGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L452VCI6 (UFBGA-100)?

Manufactured by ST, the STM32L452VCI6 is housed in a UFBGA-100 package with 100 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), A2 (PE1: Multiplexed I/O & Peripheral Pin PE1 (General)), A3 (PB8: Multiplexed I/O & Peripheral Pin PB8 (I2C)), A4 (PH3 - BOOT0 (BOOT0): Multiplexed I/O & Peripheral Pin PH3 - BOOT0 (BOOT0) (General)), A5 (PD7: Multiplexed I/O & Peripheral Pin PD7 (General)), A6 (PD5: Multiplexed I/O & Peripheral Pin PD5 (UART)).

What are the IPC-7351B PCB Footprint dimensions for STM32L452VCI6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L452VCI6 (UFBGA-100) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L452VCI6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L452VCI6 (ST, UFBGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32L452 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
A2PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
A3PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: I2C.
A4PH3 - BOOT0 (BOOT0)Digital_IOSignal terminal PH3 - BOOT0 (BOOT0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3 - BOOT0 (BOOT0). Supported peripheral buses: General.
A5PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
A6PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: UART.
A7PB4 (NJTRST)Digital_IOSignal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISOSPI3MISO. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG.
A8PB3 (JTDO/ TRACE SWO)Digital_IOSignal terminal PB3 (JTDO/ TRACE SWO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCKSPI3SCK. Supported peripheral buses: UART, SPI, SWD/JTAG.
A9PA15 (JTDI)Digital_IOSignal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_NSS_USART3RTSDE. Supported peripheral buses: UART, SPI, SWD/JTAG.
A10PA14 (JTCK/ SWCLK)Digital_IOSignal terminal PA14 (JTCK/ SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (JTCK/ SWCLK). Supported peripheral buses: I2C, SWD/JTAG.
A11PA13 (JTMS/ SWDIO)Digital_IOSignal terminal PA13 (JTMS/ SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS/ SWDIO). Supported peripheral buses: USB, SWD/JTAG.
A12PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART.
B1PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
B2PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
B3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: I2C, CAN.
B4PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART, I2C.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SCL. Supported peripheral buses: UART, I2C.
B6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
B7PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSIDFSDM1CKIN0. Supported peripheral buses: UART, SPI.
B8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISODFSDM1DATIN0. Supported peripheral buses: UART, SPI.
B9PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK_CAN1TXEVENTOUT. Supported peripheral buses: SPI, CAN.
B10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI.
B11PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
B12PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISOCOMP1OUT. Supported peripheral buses: USB, UART, SPI, PWM.
C1PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
C2PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: SPI.
C3PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
C4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSISPI3MOSI. Supported peripheral buses: UART, SPI, CAN.
C8PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
C9PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS_CAN1RXEVENTOUT. Supported peripheral buses: SPI, CAN.
C10PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISOUSART3RX. Supported peripheral buses: UART, SPI.
C11VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C12PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: USB, UART, I2C, PWM.
D1IOD1Digital_IOGeneral Purpose Digital I/O Pin IOD1
D2PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: RTC/CLK.
D3VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D10PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: PWM.
D11PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
D12PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: USB.
E1IOE1Digital_IOGeneral Purpose Digital I/O Pin IOE1
E2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E3VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E10PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
E11PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
E12PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
F1PH0 - OSC_IN (PH0)Digital_IOSignal terminal PH0 - OSC_IN (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_IN (PH0). Supported peripheral buses: RTC/CLK.
F2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F11VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F12VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
G1PH1 - OSC_ OUT (PH1)Digital_IOSignal terminal PH1 - OSC_ OUT (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_ OUT (PH1). Supported peripheral buses: RTC/CLK.
G2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G11VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G12VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H1PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: I2C, ADC.
H2NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
H3VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H10PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
H11PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
H12PD13Digital_IOSignal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: I2C.
J1VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
J2PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: I2C, ADC.
J3PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
J10PD12Digital_IOSignal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: UART, I2C.
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