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STM32F103VBI6 (UFBGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F103VBI6

STID: C1342202UFBGA-100 · 100 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F103VBI6 (UFBGA-100)A1PC14 -OSC32 A2PC13TAMPER -A3PE2A4PB9A5PB7A6PB4A7PB3A8PA15A9PA14A10PA13A11PA13A12PA12B1PC15 - OSC32B2VBATB3PE3B4PB8B5PB6B6PD5B7PD2B8PC11B9PC10B10PA12B11PC10B12PA11C1OSC_INC2VSS_5C3PE4C4PE1C5PB5C8PC12C9PA9C10PA11C11NCC12PA10D1OSC_OUTD2VDD_5D3PE5D10PA10D11PA8D12PC9E1NRSTE2PC2E3PE6E10PC7E11PC7E12PC6F1PC0F2PC1F11VSS_2F12VSS_1M12PE15M11PE14M10PE13M9PE11M8PE9M7PE7M6PB1M5PB0M4PA7M3PA4M2PA1M1VDDAL12PB12L11PB11L10PB10L9PE12L8PE10L7PE8L6PB2L5PC5L4PA6L3PA3L2PA0-WKUPL1VREF+K12PB13K11PB14K10PD12K9PD8K8PB12K5PE9K4PB1K3PA7K2PA3K1VDDAJ12PD10J11PD11J10PD13J3PA6J2PA2J1VREF+H12PD13H11PD14H10PD14H3PA5H2PA1H1VREF-G12VDD_1G11VDD_2G2PA0 WKUP -G1VSSAGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8A9A10A11A12B1B2B3B4B5B6B7B8B9B10B11B12C1C2C3C4C5C8C9C10C11C12D1D2D3D10D11D12E1E2E3E10E11E12F1F2F11F12G1G2G11G12H1H2H3H10H11H12J1J2J3J10J11J12K1K2K3K4K5K8K9K10K11K12L1L2L3L4L5L6L7L8L9L10L11L12M1M2M3M4M5M6M7M8M9M10M11M12E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PC14 -OSC32 IN(5)_I/OMultiplexed I/O & Peripheral Pin PC14 -OSC32 IN(5)_ (RTC/CLK)
A2PC13TAMPER - - RTCI/OMultiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)
A3PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
A4PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
A5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
A6PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
A7PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SWD/JTAG)
A8PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SWD/JTAG)
A9PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
A10PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
A11PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
A12PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
B1PC15 - OSC32 OUT(5)_I/OMultiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(5)_ (RTC/CLK)
B2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
B4PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
B6PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
B7PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
B8PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
B9PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
B10PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
B11PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
B12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
C1OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
C2VSS_5GNDGround Reference Pin (VSS_5)
C3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
C4PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
C5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (I2C)
C8PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
C9PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART)
C10PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, CAN)
C11NCI/OMultiplexed I/O & Peripheral Pin NC (General)
C12PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
D1OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
D2VDD_5PowerPower Supply Input (VDD_5 — 3.3V VDD (Max 4.0V))
D3PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
D10PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
D11PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
D12PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E1NRSTISystem Enable & Hardware Reset (NRST)
E2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
E3PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
E10PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E11PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E12PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
F1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
F2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
F11VSS_2GNDGround Reference Pin (VSS_2)
F12VSS_1GNDGround Reference Pin (VSS_1)
G1VSSAGNDGround Reference Pin (VSSA)
G2PA0 WKUP -I/OMultiplexed I/O & Peripheral Pin PA0 WKUP - (UART, ADC, PWM)
G11VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
G12VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
H1VREF-AnalogMultiplexed I/O & Peripheral Pin VREF- (General)
H2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
H3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC)
H10PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
H11PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
H12PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
J1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
J2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
J3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
J10PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
J11PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
J12PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
K1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
K2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC)
K3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
K4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC)
K5PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
K8PB12I/OMultiplexed I/O & Peripheral Pin PB12 (SPI, I2C)
K9PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
K10PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
K11PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
K12PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
L1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
L2PA0-WKUPI/OMultiplexed I/O & Peripheral Pin PA0-WKUP (General)
L3PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
L4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
L5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
L6PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
L7PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
L8PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
L9PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
L10PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
L11PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
L12PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
M1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
M2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
M3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
M4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
M5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
M6PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
M7PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
M8PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
M9PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
M10PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
M11PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
M12PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
PIN A1 PC14 -OSC32 IN(5)_
I/O
Multiplexed I/O & Peripheral Pin PC14 -OSC32 IN(5)_ (RTC/CLK)
Design note: PC14(6) | Alt: OSC32_IN
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F103VBI6 (ST · UFBGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F103VBI6 (UFBGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F103VBI6 (UFBGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F103VBI6 (UFBGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F103VBI6 (UFBGA-100) - 4. Package Dimensions (D×E×A)
UFBGA-100 · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F103VBI6 (UFBGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F103VBI6 (UFBGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for STM32F103
P21 · p21_fig01EXACT PACKAGE
STM32F103VBI6 (UFBGA-100) — Figure 3. STM32F103xx performance line LFBGA100 ballout
Figure 3. STM32F103xx performance line LFBGA100 ballout
P23 · p23_fig01EXACT PACKAGE
STM32F103VBI6 (UFBGA-100) — Figure 5. STM32F103xx performance line UFBGA100 pinout
Figure 5. STM32F103xx performance line UFBGA100 pinout
P78 · p78_fig02EXACT PACKAGE
STM32F103VBI6 (UFBGA-100) — Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA)
P90 · p90_fig01EXACT PACKAGE
STM32F103VBI6 (UFBGA-100) — Figure 50. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline 3%!4).'�0,!.%
Figure 50. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline 3%!4).'0,!.%
P91 · p91_fig01EXACT PACKAGE
STM32F103VBI6 (UFBGA-100) — Figure 51. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
Figure 51. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
P93 · p93_fig01EXACT PACKAGE
STM32F103VBI6 (UFBGA-100) — Figure 53. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
Figure 53. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
P94 · p94_fig01EXACT PACKAGE
STM32F103VBI6 (UFBGA-100) — Figure 54. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
Figure 54. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
P1 · p01_fig01881×629px
STM32F103VBI6 (UFBGA-100) — STM32F103x8 STM32F103xB Medium-density performance line ARM®-based 32-bit MCU with 64
STM32F103x8 STM32F103xB Medium-density performance line ARM®-based 32-bit MCU with 64
P22 · p22_fig011546×1351px
STM32F103VBI6 (UFBGA-100) — Figure 4. STM32F103xx performance line LQFP100 pinout
Figure 4. STM32F103xx performance line LQFP100 pinout
P54 · p54_fig011546×513px
STM32F103VBI6 (UFBGA-100) — Figure 24. Typical application with an 8 MHz crystal
Figure 24. Typical application with an 8 MHz crystal
P55 · p55_fig011751×683px
STM32F103VBI6 (UFBGA-100) — Figure 25. Typical application with a 32.768 kHz crystal
Figure 25. Typical application with a 32.768 kHz crystal
P55 · p55_fig01P55
STM32F103VBI6 (UFBGA-100) — Datasheet Page 55 (p55_fig01)
Datasheet Page 55 (p55_fig01)
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (STM32F103VBI6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F103VBI6 (UFBGA-100) is a 100-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
72 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.60 mm (A1=0.20 mm)
Package family: BGA (UFBGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFBGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.28 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2, C3
BOM
3× 100nF (0.1µF) 50V X7R
0402 / 0603
Digital supply decoupling caps for VDD_1..3 (Pins 24, 36, 48) — place < 1.5mm from each VDD pin.
C4
BOM
4.7µF ~ 10µF 10V X5R
0603 / 0805
Bulk decoupling capacitor for main VDD rail — place near 3.3V power entry to the MCU.
C5, C6 + FB1
BOM
100nF + 1µF + Ferrite 600Ω@100MHz
0402 / 0603
Analog rail filter for VDDA/VSSA (Pins 8, 9) 12-bit ADC — isolate digital switching noise.
Y1 + C7, C8
BOM
8MHz Crystal (CL=12pF) + 2× 18pF NP0
SMD-3225 + 0402
Main HSE oscillator crystal (Pin 5 PD0, Pin 6 PD1) — route matched traces < 4mm with GND guard ring.
STM32F103CBT6
STMicroelectronics
100% Drop-in100% Drop-in (128KB Flash Upgrade) — identical LQFP-48 pinout with doubled Flash capacity.
GD32F103C8T6
GigaDevice
Pin-to-Pin LQFP-48 (108MHz)Pin-to-Pin LQFP-48 (108MHz) — higher core clock; verify Flash wait-states & USB timing.
APM32F103C8T6
Geehy
Pin-to-Pin LQFP-48 (96MHz)Pin-to-Pin LQFP-48 (96MHz) — direct hardware replacement, register-compatible with STM32F1.

Technical Frequently Asked Questions (FAQ) — STM32F103VBI6 (UFBGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F103VBI6 (UFBGA-100)?

Manufactured by ST, the STM32F103VBI6 is housed in a UFBGA-100 package with 100 pins and a 0.50 mm lead pitch. Key pins include: A1 (PC14 -OSC32 IN(5)_: Multiplexed I/O & Peripheral Pin PC14 -OSC32 IN(5)_ (RTC/CLK)), A2 (PC13TAMPER - - RTC: Multiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)), A3 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), A4 (PB9: Multiplexed I/O & Peripheral Pin PB9 (General)), A5 (PB7: Multiplexed I/O & Peripheral Pin PB7 (I2C)), A6 (PB4: Multiplexed I/O & Peripheral Pin PB4 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32F103VBI6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103VBI6 (UFBGA-100) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103VBI6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103VBI6 (ST, UFBGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32F103 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PC14 -OSC32 IN(5)_Digital_IOSignal terminal PC14 -OSC32 IN(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14 -OSC32 IN(5)_. Supported peripheral buses: RTC/CLK.
A2PC13TAMPER - - RTCDigital_IOSignal terminal PC13TAMPER - - RTC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13TAMPER - - RTC. Supported peripheral buses: RTC/CLK.
A3PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
A4PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
A5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
A6PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
A7PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: SWD/JTAG.
A8PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: SWD/JTAG.
A9PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
A10PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
A11PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
A12PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
B1PC15 - OSC32 OUT(5)_Digital_IOSignal terminal PC15 - OSC32 OUT(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32 OUT(5)_. Supported peripheral buses: RTC/CLK.
B2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B3PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
B4PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
B6PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
B7PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
B8PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
B9PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
B10PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART, CAN.
B11PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
B12PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
C1OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
C2VSS_5GND0V electrical ground return terminal (VSS_5) for internal core logic, I/O drivers, and analog sub-blocks.
C3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
C4PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
C5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBAL. Supported peripheral buses: I2C.
C8PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
C9PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART.
C10PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: USB, UART, CAN.
C11NCNCSignal terminal NC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
C12PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
D1OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
D2VDD_5Power_InPrimary positive power supply input (VDD_5) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D3PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
D10PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
D11PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
D12PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E1NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E2PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
E3PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
E10PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E11PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E12PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
F1PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
F2PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
F11VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
F12VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
G1VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
G2PA0 WKUP -Digital_IOSignal terminal PA0 WKUP - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0 WKUP -. Supported peripheral buses: UART, ADC, PWM.
G11VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G12VDD_1Power_InPrimary positive power supply input (VDD_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
H1VREF-AnalogSignal terminal VREF- (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF-. Supported peripheral buses: General.
H2PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC.
H3PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC.
H10PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
H11PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
H12PD13Digital_IOSignal terminal PD13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
J1VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
J2PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC.
J3PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC.
J10PD13Digital_IOSignal terminal PD13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
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