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STM32F746VGH6 (TFBGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F746VGH6

STID: C1341386TFBGA-100 · 100 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F746VGH6 (TFBGA-100)A1PC14 - OSC32A2PC13A3PE2A4PB9A5PB7A6PB4(NJTRST)A7PB3(JTDO/TRAA8PA15(JT DI)A9PA14(JT CK -A10PA13(JT MS -B1IOB1B2VBATB3PE3B4PB8B5PB6B6PD5B7PD2B8PC11B9PC10B10PA12C1PH0 - OSC INC2VSSC3PE4C4PE1C5PB5C6PD6C7PD3C8PC12C9PA9C10PA11D1PH1 - OSC_OUD2VDDD3PE5D4PE0D5BOOTD6PD7D7PD4D8PD0D9PA8D10PA10E1NRSTE2PC2E3PE6E4VSSE5VSSE6BYPASS_REGE7VCAP_2E8PD1E9PC9E10PC7K10PD12K9PD8K8PB12K7PB11K6PE13K5PE9K4PB1K3PA7K2PA3K1VDDJ10PD13J9PD9J8PB13J7PB10J6PE12J5PE8J4PB0J3PA6J2PA2J1VSSH10PB14H9PD10H8PD14H7PE15H6PE11H5PE7H4PC5H3PA5H2PA1H1VDDAG10PB15G9PD11G8PD15G7PE14G6PE10G5PB2G4PC4G3PA4G2PA0 - WKUP(PG1VSSAF10PC6F9PC8F8VCAP_1F7PDR_ONF6VDDUSBF5VDDF4VDDF3PC3F2PC1F1PC0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1A2B2C2D2E2F2G2H2J2K2A3B3C3D3E3F3G3H3J3K3A4B4C4D4E4F4G4H4J4K4A5B5C5D5E5F5G5H5J5K5A6B6C6D6E6F6G6H6J6K6A7B7C7D7E7F7G7H7J7K7A8B8C8D8E8F8G8H8J8K8A9B9C9D9E9F9G9H9J9K9A10B10C10D10E10F10G10H10J10K10E=8.00mm · Pitch e=0.80mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PC14 - OSC32_I N(PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_I N(PC14) (RTC/CLK)
A2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
A3PE2I/OMultiplexed I/O & Peripheral Pin PE2 (SPI)
A4PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
A5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
A6PB4(NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4(NJTRST) (SWD/JTAG)
A7PB3(JTDO/TRACESWO)I/OMultiplexed I/O & Peripheral Pin PB3(JTDO/TRACESWO) (SWD/JTAG)
A8PA15(JT DI)I/OMultiplexed I/O & Peripheral Pin PA15(JT DI) (UART, SPI, SWD/JTAG)
A9PA14(JT CK - SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14(JT CK - SWCLK) (SWD/JTAG)
A10PA13(JT MS - SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13(JT MS - SWDIO) (SWD/JTAG)
B1IOB1I/OGeneral Purpose Digital I/O Pin IOB1
B2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
B4PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
B6PD5I/OMultiplexed I/O & Peripheral Pin PD5 (UART)
B7PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
B8PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
B9PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
B10PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART)
C1PH0 - OSC IN(_ PH0)I/OMultiplexed I/O & Peripheral Pin PH0 - OSC IN(_ PH0) (RTC/CLK)
C2VSSGNDGround Reference Pin (VSS)
C3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (SPI)
C4PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
C5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
C6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (UART, SPI, I2C)
C7PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART, SPI)
C8PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
C9PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, SPI, PWM)
C10PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, PWM, CAN)
D1PH1 - OSC_OU T(PH1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC_OU T(PH1) (RTC/CLK)
D2VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D3PE5I/OMultiplexed I/O & Peripheral Pin PE5 (SPI)
D4PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
D5BOOTI/OMultiplexed I/O & Peripheral Pin BOOT (General)
D6PD7I/OMultiplexed I/O & Peripheral Pin PD7 (UART)
D7PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART)
D8PD0I/OMultiplexed I/O & Peripheral Pin PD0 (CAN)
D9PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
D10PA10I/OMultiplexed I/O & Peripheral Pin PA10 (PWM)
E1NRSTISystem Enable & Hardware Reset (NRST)
E2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
E3PE6I/OMultiplexed I/O & Peripheral Pin PE6 (I2C, PWM)
E4VSSGNDGround Reference Pin (VSS)
E5VSSGNDGround Reference Pin (VSS)
E6BYPASS_REGI/OMultiplexed I/O & Peripheral Pin BYPASS_REG (General)
E7VCAP_2I/OMultiplexed I/O & Peripheral Pin VCAP_2 (General)
E8PD1I/OMultiplexed I/O & Peripheral Pin PD1 (CAN)
E9PC9I/OMultiplexed I/O & Peripheral Pin PC9 (PWM, RTC/CLK)
E10PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
F1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
F2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, ADC, RTC/CLK)
F3PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
F4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F6VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
F7PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
F8VCAP_1I/OMultiplexed I/O & Peripheral Pin VCAP_1 (General)
F9PC8I/OMultiplexed I/O & Peripheral Pin PC8 (UART, PWM)
F10PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
G1VSSAGNDGround Reference Pin (VSSA)
G2PA0 - WKUP(P A0)I/OMultiplexed I/O & Peripheral Pin PA0 - WKUP(P A0) (UART, ADC, PWM)
G3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
G4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
G5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI, I2C)
G6PE10I/OMultiplexed I/O & Peripheral Pin PE10 (UART, PWM)
G7PE14I/OMultiplexed I/O & Peripheral Pin PE14 (PWM)
G8PD15I/OMultiplexed I/O & Peripheral Pin PD15 (PWM)
G9PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART, I2C)
G10PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
H1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
H2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
H3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
H4PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
H5PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
H6PE11I/OMultiplexed I/O & Peripheral Pin PE11 (PWM)
H7PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
H8PD14I/OMultiplexed I/O & Peripheral Pin PD14 (PWM)
H9PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART)
H10PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
J1VSSGNDGround Reference Pin (VSS)
J2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (SPI, ADC, PWM)
J3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (ADC)
J4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC, PWM)
J5PE8I/OMultiplexed I/O & Peripheral Pin PE8 (PWM)
J6PE12I/OMultiplexed I/O & Peripheral Pin PE12 (SPI, PWM)
J7PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, PWM)
J8PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM, CAN)
J9PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
J10PD13I/OMultiplexed I/O & Peripheral Pin PD13 (SPI, PWM)
K1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
K2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (ADC, PWM)
K3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
K4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
K5PE9I/OMultiplexed I/O & Peripheral Pin PE9 (PWM)
K6PE13I/OMultiplexed I/O & Peripheral Pin PE13 (PWM)
K7PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, PWM)
K8PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI)
K9PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
K10PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART, I2C, PWM)
PIN A1 PC14 - OSC32_I N(PC14)
I/O
Multiplexed I/O & Peripheral Pin PC14 - OSC32_I N(PC14) (RTC/CLK)
Design note: Alt: EVENTOUT | Add: OSC32_IN
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F746VGH6 (ST · TFBGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F746VGH6 (TFBGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F746VGH6 (TFBGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F746VGH6 (TFBGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F746VGH6 (TFBGA-100) - 4. Package Dimensions (D×E×A)
TFBGA-100 · 8.00×8.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F746VGH6 (TFBGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F746VGH6 (TFBGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for STM32F745 / STM32F746
P46 · p46_fig01EXACT PACKAGE
STM32F746VGH6 (TFBGA-100) — Figure 12. STM32F74xVx TFBGA100 ballout
Figure 12. STM32F74xVx TFBGA100 ballout
P198 · p198_fig01EXACT PACKAGE
STM32F746VGH6 (TFBGA-100) — Figure 80. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
Figure 80. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
P198 · p198_fig02EXACT PACKAGE
STM32F746VGH6 (TFBGA-100) — Figure 81. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
Figure 81. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
P199 · p199_fig01EXACT PACKAGE
STM32F746VGH6 (TFBGA-100) — Figure 82. TFBGA100, 8 × 8 × 0.8 mm thin fine-pitch ball grid array
Figure 82. TFBGA100, 8 × 8 × 0.8 mm thin fine-pitch ball grid array
P200 · p200_fig01EXACT PACKAGE
STM32F746VGH6 (TFBGA-100) — Figure 83. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array
Figure 83. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array
P201 · p201_fig01EXACT PACKAGE
STM32F746VGH6 (TFBGA-100) — Figure 84. TFBGA100, 8 × 8 × 0.8mm thin fine-pitch ball grid array package
Figure 84. TFBGA100, 8 × 8 × 0.8mm thin fine-pitch ball grid array package
P1 · p01_fig01881×410px
STM32F746VGH6 (TFBGA-100) — ARM®-based Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 1MB Flash/320+16+ 4KB
ARM®-based Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 1MB Flash/320+16+ 4KB
P45 · p45_fig011546×1389px
STM32F746VGH6 (TFBGA-100) — Figure 11. STM32F74xVx LQFP100 pinout
Figure 11. STM32F74xVx LQFP100 pinout
P46 · p46_fig01P46
STM32F746VGH6 (TFBGA-100) — Datasheet Page 46 (p46_fig01)
Datasheet Page 46 (p46_fig01)
P95 · p95_fig011751×1690px
STM32F746VGH6 (TFBGA-100) — Figure 22. Power supply scheme sd
Figure 22. Power supply scheme sd
P95 · p95_fig01P95
STM32F746VGH6 (TFBGA-100) — Datasheet Page 95 (p95_fig01)
Datasheet Page 95 (p95_fig01)
P125 · p125_fig011546×487px
STM32F746VGH6 (TFBGA-100) — Figure 32. Typical application with an 8 MHz crystal
Figure 32. Typical application with an 8 MHz crystal
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (STM32F746VGH6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F746VGH6 (TFBGA-100) is a 100-pin embedded microcontroller unit (mcu) featuring a 8.00 × 8.00 × 1.10 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, CAN, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
216 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
72 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 1.10 mm (A1=0.25 mm)
Package family: BGA (TFBGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, CAN, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TFBGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.10mm · e=0.80mm
Pad Size (W × L)Level B
0.32 × 0.32 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-100
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F746VGH6 (TFBGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F746VGH6 (TFBGA-100)?

Manufactured by ST, the STM32F746VGH6 is housed in a TFBGA-100 package with 100 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: A1 (PC14 - OSC32_I N(PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC32_I N(PC14) (RTC/CLK)), A2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), A3 (PE2: Multiplexed I/O & Peripheral Pin PE2 (SPI)), A4 (PB9: Multiplexed I/O & Peripheral Pin PB9 (General)), A5 (PB7: Multiplexed I/O & Peripheral Pin PB7 (General)), A6 (PB4(NJTRST): Multiplexed I/O & Peripheral Pin PB4(NJTRST) (SWD/JTAG)).

What are the IPC-7351B PCB Footprint dimensions for STM32F746VGH6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F746VGH6 (TFBGA-100) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.80 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F746VGH6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F746VGH6 (ST, TFBGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32F745 / STM32F746 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PC14 - OSC32_I N(PC14)Digital_IOSignal terminal PC14 - OSC32_I N(PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_I N(PC14). Supported peripheral buses: RTC/CLK.
A2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
A3PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCK. Supported peripheral buses: SPI.
A4PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
A5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
A6PB4(NJTRST)Digital_IOSignal terminal PB4(NJTRST) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4(NJTRST). Supported peripheral buses: SWD/JTAG.
A7PB3(JTDO/TRACESWO)Digital_IOSignal terminal PB3(JTDO/TRACESWO) (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3(JTDO/TRACESWO). Supported peripheral buses: SWD/JTAG.
A8PA15(JT DI)Digital_IOSignal terminal PA15(JT DI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
A9PA14(JT CK - SWCLK)Digital_IOSignal terminal PA14(JT CK - SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14(JT CK - SWCLK). Supported peripheral buses: SWD/JTAG.
A10PA13(JT MS - SWDIO)Digital_IOSignal terminal PA13(JT MS - SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JT MS - SWDIO). Supported peripheral buses: SWD/JTAG.
B1IOB1Digital_IOGeneral Purpose Digital I/O Pin IOB1
B2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B3PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
B4PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
B6PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: UART.
B7PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
B8PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI.
B9PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
B10PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART.
C1PH0 - OSC IN(_ PH0)Digital_IOSignal terminal PH0 - OSC IN(_ PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC IN(_ PH0). Supported peripheral buses: RTC/CLK.
C2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS. Supported peripheral buses: SPI.
C4PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
C5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
C6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI, I2C.
C7PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI.
C8PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI.
C9PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
C10PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART, PWM, CAN.
D1PH1 - OSC_OU T(PH1)Digital_IOSignal terminal PH1 - OSC_OU T(PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_OU T(PH1). Supported peripheral buses: RTC/CLK.
D2VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D3PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO. Supported peripheral buses: SPI.
D4PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
D5BOOTDigital_IOSignal terminal BOOT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT. Supported peripheral buses: General.
D6PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: UART.
D7PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: UART.
D8PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: CAN.
D9PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
D10PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: PWM.
E1NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E2PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC.
E3PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: I2C, PWM.
E4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E6BYPASS_REGDigital_IOSignal terminal BYPASS_REG (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: BYPASS_REG. Supported peripheral buses: General.
E7VCAP_2Digital_IOSignal terminal VCAP_2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_2. Supported peripheral buses: General.
E8PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: CAN.
E9PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: PWM, RTC/CLK.
E10PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
F1PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
F2PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC, RTC/CLK.
F3PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC.
F4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F6VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F7PDR_ONDigital_IOSignal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
F8VCAP_1Digital_IOSignal terminal VCAP_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_1. Supported peripheral buses: General.
F9PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: UART, PWM.
F10PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
G1VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
G2PA0 - WKUP(P A0)Digital_IOSignal terminal PA0 - WKUP(P A0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0 - WKUP(P A0). Supported peripheral buses: UART, ADC, PWM.
G3PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
G4PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART, ADC.
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