Mechanical Dimensions & Land Pattern (UFBGA-169)
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit UFBGA-169 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32L496AGI6P (UFBGA-169)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32L496AGI6P (UFBGA-169)?
Manufactured by ST, the STM32L496AGI6P is housed in a UFBGA-169 package with 169 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PI10: Multiplexed I/O & Peripheral Pin PI10 (General)), A2 (PH2: Multiplexed I/O & Peripheral Pin PH2 (General)), A3 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), A4 (PE0: Multiplexed I/O & Peripheral Pin PE0 (General)), A5 (PB4 (NJTRST): Multiplexed I/O & Peripheral Pin PB4 (NJTRST) (UART, SPI, I2C, SWD/JTAG)), A6 (PB3 (JTDO/TRAC ESWO): Multiplexed I/O & Peripheral Pin PB3 (JTDO/TRAC ESWO) (UART, SPI, PWM, SWD/JTAG)).
What are the IPC-7351B PCB Footprint dimensions for STM32L496AGI6P?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L496AGI6P (UFBGA-169) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 169 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L496AGI6P?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L496AGI6P (ST, UFBGA-169) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (169 pins) & STM32L496 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| A1 | PI10 | Digital_IO | Signal terminal PI10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI10. Supported peripheral buses: General. |
| A2 | PH2 | Digital_IO | Signal terminal PH2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH2. Supported peripheral buses: General. |
| A3 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| A4 | PE0 | Digital_IO | Signal terminal PE0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General. |
| A5 | PB4 (NJTRST) | Digital_IO | Signal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG. |
| A6 | PB3 (JTDO/TRAC ESWO) | Digital_IO | Signal terminal PB3 (JTDO/TRAC ESWO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI, PWM, SWD/JTAG. |
| A7 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| A8 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| A9 | PA15(JTDI) | Digital_IO | Signal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSSSPI3NSS. Supported peripheral buses: UART, SPI, SWD/JTAG. |
| A10 | PA14(JTCK/ SWCLK) | Digital_IO | Signal terminal PA14(JTCK/ SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, I2C4_SMBA. Supported peripheral buses: I2C, SWD/JTAG. |
| A11 | PA13(JTMS/ SWDIO) | Digital_IO | Signal terminal PA13(JTMS/ SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JTMS/ SWDIO). Supported peripheral buses: SWD/JTAG. |
| A12 | PI0 | Digital_IO | Signal terminal PI0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI0. Supported peripheral buses: PWM. |
| A13 | PH14 | Digital_IO | Signal terminal PH14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH14. Supported peripheral buses: PWM. |
| B1 | PI9 | Digital_IO | Signal terminal PI9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI9. Supported peripheral buses: CAN. |
| B2 | PI7 | Digital_IO | Signal terminal PI7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI7. Supported peripheral buses: PWM. |
| B3 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| B4 | PE1 | Digital_IO | Signal terminal PE1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General. |
| B5 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSISPI3MOSI. Supported peripheral buses: UART, SPI, CAN. |
| B6 | VDDIO2 | Power_In | Primary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| B7 | PG9 | Digital_IO | Signal terminal PG9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCKUSART1TX. Supported peripheral buses: SPI. |
| B8 | PD0 | Digital_IO | Signal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, CAN. |
| B9 | PI6 | Digital_IO | Signal terminal PI6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI6. Supported peripheral buses: PWM. |
| B10 | PI2 | Digital_IO | Signal terminal PI2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI2. Supported peripheral buses: PWM. |
| B11 | PI1 | Digital_IO | Signal terminal PI1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKDCMID8. Supported peripheral buses: SPI. |
| B12 | PH15 | Digital_IO | Signal terminal PH15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH15. Supported peripheral buses: PWM. |
| B13 | PH12 | Digital_IO | Signal terminal PH12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH12. Supported peripheral buses: PWM. |
| C1 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| C2 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| C3 | PI11 | Digital_IO | Signal terminal PI11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI11. Supported peripheral buses: General. |
| C4 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: UART, PWM, CAN. |
| C5 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART, I2C, PWM. |
| C6 | PG15 | Digital_IO | Signal terminal PG15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PG15. Supported peripheral buses: I2C. |
| C7 | PD4 | Digital_IO | Signal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: UART, SPI. |
| C8 | PD1 | Digital_IO | Signal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI, CAN. |
| C9 | PH13 | Digital_IO | Signal terminal PH13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH13. Supported peripheral buses: PWM. |
| C10 | PI3 | Digital_IO | Signal terminal PI3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI3. Supported peripheral buses: General. |
| C11 | PI8 | Digital_IO | Signal terminal PI8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI8. Supported peripheral buses: General. |
| C12 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| C13 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| D1 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General. |
| D2 | PE3 | Digital_IO | Signal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General. |
| D3 | PE2 | Digital_IO | Signal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General. |
| D4 | PB9 | Digital_IO | Signal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: UART, I2C, CAN. |
| D5 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SDA. Supported peripheral buses: UART, I2C. |
| D6 | PG10 | Digital_IO | Signal terminal PG10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI. |
| D7 | PD5 | Digital_IO | Signal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: UART. |
| D8 | PD2 | Digital_IO | Signal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART. |
| D9 | PC10 | Digital_IO | Signal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI. |
| D10 | PI4 | Digital_IO | Signal terminal PI4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI4. Supported peripheral buses: General. |
| D11 | PH9 | Digital_IO | Signal terminal PH9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH9. Supported peripheral buses: I2C. |
| D12 | PH7 | Digital_IO | Signal terminal PH7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH7. Supported peripheral buses: I2C. |
| D13 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART, CAN. |
| E1 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| E2 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| E3 | PE6 | Digital_IO | Signal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: I2C, RTC/CLK. |
| E4 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General. |
| E5 | PH3BOOT0 - | Digital_IO | Signal terminal PH3BOOT0 - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3BOOT0 -. Supported peripheral buses: General. |
| E6 | PG11 | Digital_IO | Signal terminal PG11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI. |
| E7 | PD6 | Digital_IO | Signal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: UART, I2C. |
| E8 | PD3 | Digital_IO | Signal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKDCMID5, SPI2_MISO. Supported peripheral buses: UART, SPI. |
| E9 | PC11 | Digital_IO | Signal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI. |
| E10 | PI5 | Digital_IO | Signal terminal PI5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PI5. Supported peripheral buses: PWM. |
| E11 | PH6 | Digital_IO | Signal terminal PH6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH6. Supported peripheral buses: I2C. |
| E12 | VDDUSB | Power_In | Primary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |










