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C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) — Symbol, Footprint IPC-7351B & 3D STEP Model

C1340622

SemiconductorTFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB · 100 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)A1PB1/AD5A2PC29A3VDDIOA4PB9/PGMCK/XIA5PB8/XOUTA6PB13/DAC0A7DDP/PB11A8DDM/PB10A9TMS/SWDIO/PBA10JTAGSELB1PC30B2ADVREFB3GNDANAB4PB14/DAC1B5PC21B6PC20B7PA31B8PC19B9PC18B10TDO/TRACESWOC1PB2/AD6C2PB2/AD6C3PC25C4PC23C5ERASE/PB12C6TCK/SWCLK/PBC7PC16C8PA1/PGMEN1C9PC17C10PA0/PGMEN0D1PB3/AD7D2PB0/AD4D3PC24D4PC22D5GNDD6GNDD7VDDCORED8PA2/PGMEN2D9PC11D10PC14E1PA17/PGMD5/AE2PC31E3VDDINE4GNDE5GNDE6NRSTE7PA29/AD13E8PA30/AD14E9PC10E10PA3K10PA7/XIN32/PGK9PA8/XOUT32/PK8PA9/PGMM1K7PC2K6PC3K5PC5K4PA20/PGMD8/AK3PC12/AD12K2PC13/AD10K1PA22/PGMD10/J10VDDIOJ9VDDCOREJ8GNDJ7PA10/PGMM2J6PA25/PGMD13J5PA24/PGMD12J4PC6J3PA16/PGMD4J2PC0J1PC15/AD11H10TDI/PB4H9PA6/PGMNOEH8PC1H7PA11/PGMM3H6PC4H5PA13/PGMD1H4PA14/PGMD2H3PC7H2PA23/PGMD11H1PA19/PGMD7/AG10PA5/PGMRDYG9PA4/PGMNCMDG8PC28G7PA12/PGMD0G6PA26/PGMD14G5VDDCOREG4VDDCOREG3PA15/PGMD3G2PC27G1PA21/PGMD9/AF10PC9F9TSTF8PA28F7PC8F6PA27/PGMD15F5VDDIOF4GNDF3VDDOUTF2PC26F1PA18/PGMD6/AGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.268.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1A2A3A4A5A6A7A8A9A10B1B2B3B4B5B6B7B8B9B10C1C2C3C4C5C6C7C8C9C10D1D2D3D4D5D6D7D8D9D10E1E2E3E4E5E6E7E8E9E10F1F2F3F4F5F6F7F8F9F10G1G2G3G4G5G6G7G8G9G10H1H2H3H4H5H6H7H8H9H10J1J2J3J4J5J6J7J8J9J10K1K2K3K4K5K6K7K8K9K10E=9.00mm · Pitch e=0.80mmD=9.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 9.00mm × 9.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PB1/AD5I/OMultiplexed I/O & Peripheral Pin PB1/AD5 (General)
A2PC29I/OMultiplexed I/O & Peripheral Pin PC29 (General)
A3VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
A4PB9/PGMCK/XINI/OMultiplexed I/O & Peripheral Pin PB9/PGMCK/XIN (RTC/CLK)
A5PB8/XOUTI/OMultiplexed I/O & Peripheral Pin PB8/XOUT (RTC/CLK)
A6PB13/DAC0I/OMultiplexed I/O & Peripheral Pin PB13/DAC0 (DAC)
A7DDP/PB11I/OMultiplexed I/O & Peripheral Pin DDP/PB11 (General)
A8DDM/PB10I/OMultiplexed I/O & Peripheral Pin DDM/PB10 (General)
A9TMS/SWDIO/PB6I/OMultiplexed I/O & Peripheral Pin TMS/SWDIO/PB6 (SWD/JTAG)
A10JTAGSELI/OMultiplexed I/O & Peripheral Pin JTAGSEL (SWD/JTAG)
B1PC30I/OMultiplexed I/O & Peripheral Pin PC30 (General)
B2ADVREFI/OMultiplexed I/O & Peripheral Pin ADVREF (General)
B3GNDANAGNDGround Reference Pin (GNDANA)
B4PB14/DAC1I/OMultiplexed I/O & Peripheral Pin PB14/DAC1 (DAC)
B5PC21I/OMultiplexed I/O & Peripheral Pin PC21 (General)
B6PC20I/OMultiplexed I/O & Peripheral Pin PC20 (General)
B7PA31I/OMultiplexed I/O & Peripheral Pin PA31 (General)
B8PC19I/OMultiplexed I/O & Peripheral Pin PC19 (General)
B9PC18I/OMultiplexed I/O & Peripheral Pin PC18 (General)
B10TDO/TRACESWO/PB5I/OMultiplexed I/O & Peripheral Pin TDO/TRACESWO/PB5 (General)
C1PB2/AD6I/OMultiplexed I/O & Peripheral Pin PB2/AD6 (General)
C2PB2/AD6I/OMultiplexed I/O & Peripheral Pin PB2/AD6 (General)
C3PC25I/OMultiplexed I/O & Peripheral Pin PC25 (General)
C4PC23I/OMultiplexed I/O & Peripheral Pin PC23 (General)
C5ERASE/PB12I/OMultiplexed I/O & Peripheral Pin ERASE/PB12 (General)
C6TCK/SWCLK/PB7I/OMultiplexed I/O & Peripheral Pin TCK/SWCLK/PB7 (SWD/JTAG)
C7PC16I/OMultiplexed I/O & Peripheral Pin PC16 (General)
C8PA1/PGMEN1I/OMultiplexed I/O & Peripheral Pin PA1/PGMEN1 (General)
C9PC17I/OMultiplexed I/O & Peripheral Pin PC17 (General)
C10PA0/PGMEN0I/OMultiplexed I/O & Peripheral Pin PA0/PGMEN0 (General)
D1PB3/AD7I/OMultiplexed I/O & Peripheral Pin PB3/AD7 (General)
D2PB0/AD4I/OMultiplexed I/O & Peripheral Pin PB0/AD4 (General)
D3PC24I/OMultiplexed I/O & Peripheral Pin PC24 (General)
D4PC22I/OMultiplexed I/O & Peripheral Pin PC22 (General)
D5GNDGNDGround Reference Pin (GND)
D6GNDGNDGround Reference Pin (GND)
D7VDDCOREPowerPower Supply Input (VDDCORE — 3.3V / 5.0V Standard Logic)
D8PA2/PGMEN2I/OMultiplexed I/O & Peripheral Pin PA2/PGMEN2 (General)
D9PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
D10PC14I/OMultiplexed I/O & Peripheral Pin PC14 (General)
E1PA17/PGMD5/AD0I/OMultiplexed I/O & Peripheral Pin PA17/PGMD5/AD0 (General)
E2PC31I/OMultiplexed I/O & Peripheral Pin PC31 (General)
E3VDDINPowerPower Supply Input (VDDIN — 3.3V / 5.0V Standard Logic)
E4GNDGNDGround Reference Pin (GND)
E5GNDGNDGround Reference Pin (GND)
E6NRSTISystem Enable & Hardware Reset (NRST)
E7PA29/AD13I/OMultiplexed I/O & Peripheral Pin PA29/AD13 (General)
E8PA30/AD14I/OMultiplexed I/O & Peripheral Pin PA30/AD14 (General)
E9PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
E10PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
F1PA18/PGMD6/AD1I/OMultiplexed I/O & Peripheral Pin PA18/PGMD6/AD1 (General)
F2PC26I/OMultiplexed I/O & Peripheral Pin PC26 (General)
F3VDDOUTPowerPower Supply Input (VDDOUT — 3.3V / 5.0V Standard Logic)
F4GNDGNDGround Reference Pin (GND)
F5VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
F6PA27/PGMD15I/OMultiplexed I/O & Peripheral Pin PA27/PGMD15 (General)
F7PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F8PA28I/OMultiplexed I/O & Peripheral Pin PA28 (General)
F9TSTI/OMultiplexed I/O & Peripheral Pin TST (General)
F10PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
G1PA21/PGMD9/AD8I/OMultiplexed I/O & Peripheral Pin PA21/PGMD9/AD8 (General)
G2PC27I/OMultiplexed I/O & Peripheral Pin PC27 (General)
G3PA15/PGMD3I/OMultiplexed I/O & Peripheral Pin PA15/PGMD3 (General)
G4VDDCOREPowerPower Supply Input (VDDCORE — 3.3V / 5.0V Standard Logic)
G5VDDCOREPowerPower Supply Input (VDDCORE — 3.3V / 5.0V Standard Logic)
G6PA26/PGMD14I/OMultiplexed I/O & Peripheral Pin PA26/PGMD14 (General)
G7PA12/PGMD0I/OMultiplexed I/O & Peripheral Pin PA12/PGMD0 (General)
G8PC28I/OMultiplexed I/O & Peripheral Pin PC28 (General)
G9PA4/PGMNCMDI/OMultiplexed I/O & Peripheral Pin PA4/PGMNCMD (General)
G10PA5/PGMRDYI/OMultiplexed I/O & Peripheral Pin PA5/PGMRDY (General)
H1PA19/PGMD7/AD2I/OMultiplexed I/O & Peripheral Pin PA19/PGMD7/AD2 (General)
H2PA23/PGMD11I/OMultiplexed I/O & Peripheral Pin PA23/PGMD11 (General)
H3PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
H4PA14/PGMD2I/OMultiplexed I/O & Peripheral Pin PA14/PGMD2 (General)
H5PA13/PGMD1I/OMultiplexed I/O & Peripheral Pin PA13/PGMD1 (General)
H6PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
H7PA11/PGMM3I/OMultiplexed I/O & Peripheral Pin PA11/PGMM3 (General)
H8PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
H9PA6/PGMNOEI/OMultiplexed I/O & Peripheral Pin PA6/PGMNOE (General)
H10TDI/PB4I/OMultiplexed I/O & Peripheral Pin TDI/PB4 (General)
J1PC15/AD11I/OMultiplexed I/O & Peripheral Pin PC15/AD11 (General)
J2PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
J3PA16/PGMD4I/OMultiplexed I/O & Peripheral Pin PA16/PGMD4 (General)
J4PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
J5PA24/PGMD12I/OMultiplexed I/O & Peripheral Pin PA24/PGMD12 (General)
J6PA25/PGMD13I/OMultiplexed I/O & Peripheral Pin PA25/PGMD13 (General)
J7PA10/PGMM2I/OMultiplexed I/O & Peripheral Pin PA10/PGMM2 (General)
J8GNDGNDGround Reference Pin (GND)
J9VDDCOREPowerPower Supply Input (VDDCORE — 3.3V / 5.0V Standard Logic)
J10VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
K1PA22/PGMD10/AD9I/OMultiplexed I/O & Peripheral Pin PA22/PGMD10/AD9 (General)
K2PC13/AD10I/OMultiplexed I/O & Peripheral Pin PC13/AD10 (General)
K3PC12/AD12I/OMultiplexed I/O & Peripheral Pin PC12/AD12 (General)
K4PA20/PGMD8/AD3I/OMultiplexed I/O & Peripheral Pin PA20/PGMD8/AD3 (General)
K5PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
K6PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
K7PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
K8PA9/PGMM1I/OMultiplexed I/O & Peripheral Pin PA9/PGMM1 (General)
K9PA8/XOUT32/PGMM0I/OMultiplexed I/O & Peripheral Pin PA8/XOUT32/PGMM0 (RTC/CLK)
K10PA7/XIN32/PGMNVALIDI/OMultiplexed I/O & Peripheral Pin PA7/XIN32/PGMNVALID (RTC/CLK)
PIN A1 PB1/AD5
I/O
Multiplexed I/O & Peripheral Pin PB1/AD5 (General)
Design note: Signal terminal PB1/AD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/AD5. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C1340622 (Semiconductor · TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 4. Package Dimensions (D×E×A)
TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB · 9.00×9.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C1340622)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) is a 100-pin standard electronic & interconnect component featuring a 9.00 × 9.00 × 1.12 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated DAC, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.00 × 9.00 × 1.12 mm (A1=0.25 mm)
Package family: BGA (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
DAC, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 9.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.12mm · e=0.80mm
Pad Size (W × L)Level B
0.40 × 0.40 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB)?

Manufactured by Semiconductor, the C1340622 is housed in a TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB package with 100 pins and a 0.80 mm lead pitch. Key pins include: A1 (PB1/AD5: Multiplexed I/O & Peripheral Pin PB1/AD5 (General)), A2 (PC29: Multiplexed I/O & Peripheral Pin PC29 (General)), A3 (VDDIO: Power Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)), A4 (PB9/PGMCK/XIN: Multiplexed I/O & Peripheral Pin PB9/PGMCK/XIN (RTC/CLK)), A5 (PB8/XOUT: Multiplexed I/O & Peripheral Pin PB8/XOUT (RTC/CLK)), A6 (PB13/DAC0: Multiplexed I/O & Peripheral Pin PB13/DAC0 (DAC)).

What are the IPC-7351B PCB Footprint dimensions for C1340622?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C1340622 (TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) has a nominal body envelope of 9.00 × 9.00 mm, pitch e = 0.80 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C1340622?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C1340622 (Semiconductor, TFBGA-100_L9.0-W9.0-R10-C10-P0.80-TL_MICROCHIP_ATSAM3S1CB) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & C1340622 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PB1/AD5Digital_IOSignal terminal PB1/AD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1/AD5. Supported peripheral buses: General.
A2PC29Digital_IOSignal terminal PC29 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC29. Supported peripheral buses: General.
A3VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
A4PB9/PGMCK/XINDigital_IOSignal terminal PB9/PGMCK/XIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB9/PGMCK/XIN. Supported peripheral buses: RTC/CLK.
A5PB8/XOUTDigital_IOSignal terminal PB8/XOUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB8/XOUT. Supported peripheral buses: RTC/CLK.
A6PB13/DAC0Digital_IOSignal terminal PB13/DAC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB13/DAC0. Supported peripheral buses: DAC.
A7DDP/PB11Digital_IOSignal terminal DDP/PB11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDP/PB11. Supported peripheral buses: General.
A8DDM/PB10Digital_IOSignal terminal DDM/PB10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DDM/PB10. Supported peripheral buses: General.
A9TMS/SWDIO/PB6Digital_IOSignal terminal TMS/SWDIO/PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TMS/SWDIO/PB6. Supported peripheral buses: SWD/JTAG.
A10JTAGSELDigital_IOSignal terminal JTAGSEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: JTAGSEL. Supported peripheral buses: SWD/JTAG.
B1PC30Digital_IOSignal terminal PC30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC30. Supported peripheral buses: General.
B2ADVREFDigital_IOSignal terminal ADVREF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ADVREF. Supported peripheral buses: General.
B3GNDANAGND0V electrical ground return terminal (GNDANA) for internal core logic, I/O drivers, and analog sub-blocks.
B4PB14/DAC1Digital_IOSignal terminal PB14/DAC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14/DAC1. Supported peripheral buses: DAC.
B5PC21Digital_IOSignal terminal PC21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC21. Supported peripheral buses: General.
B6PC20Digital_IOSignal terminal PC20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC20. Supported peripheral buses: General.
B7PA31Digital_IOSignal terminal PA31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA31. Supported peripheral buses: General.
B8PC19Digital_IOSignal terminal PC19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC19. Supported peripheral buses: General.
B9PC18Digital_IOSignal terminal PC18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC18. Supported peripheral buses: General.
B10TDO/TRACESWO/PB5Digital_IOSignal terminal TDO/TRACESWO/PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TDO/TRACESWO/PB5. Supported peripheral buses: General.
C1PB2/AD6Digital_IOSignal terminal PB2/AD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2/AD6. Supported peripheral buses: General.
C2PB2/AD6Digital_IOSignal terminal PB2/AD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2/AD6. Supported peripheral buses: General.
C3PC25Digital_IOSignal terminal PC25 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC25. Supported peripheral buses: General.
C4PC23Digital_IOSignal terminal PC23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC23. Supported peripheral buses: General.
C5ERASE/PB12Digital_IOSignal terminal ERASE/PB12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ERASE/PB12. Supported peripheral buses: General.
C6TCK/SWCLK/PB7Digital_IOSignal terminal TCK/SWCLK/PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TCK/SWCLK/PB7. Supported peripheral buses: SWD/JTAG.
C7PC16Digital_IOSignal terminal PC16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC16. Supported peripheral buses: General.
C8PA1/PGMEN1Digital_IOSignal terminal PA1/PGMEN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1/PGMEN1. Supported peripheral buses: General.
C9PC17Digital_IOSignal terminal PC17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC17. Supported peripheral buses: General.
C10PA0/PGMEN0Digital_IOSignal terminal PA0/PGMEN0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0/PGMEN0. Supported peripheral buses: General.
D1PB3/AD7Digital_IOSignal terminal PB3/AD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB3/AD7. Supported peripheral buses: General.
D2PB0/AD4Digital_IOSignal terminal PB0/AD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0/AD4. Supported peripheral buses: General.
D3PC24Digital_IOSignal terminal PC24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC24. Supported peripheral buses: General.
D4PC22Digital_IOSignal terminal PC22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC22. Supported peripheral buses: General.
D5GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
D6GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
D7VDDCOREPower_InPrimary positive power supply input (VDDCORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
D8PA2/PGMEN2Digital_IOSignal terminal PA2/PGMEN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2/PGMEN2. Supported peripheral buses: General.
D9PC11Digital_IOSignal terminal PC11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
D10PC14Digital_IOSignal terminal PC14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC14. Supported peripheral buses: General.
E1PA17/PGMD5/AD0Digital_IOSignal terminal PA17/PGMD5/AD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA17/PGMD5/AD0. Supported peripheral buses: General.
E2PC31Digital_IOSignal terminal PC31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC31. Supported peripheral buses: General.
E3VDDINPower_InPrimary positive power supply input (VDDIN) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
E4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
E5GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
E6NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E7PA29/AD13Digital_IOSignal terminal PA29/AD13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA29/AD13. Supported peripheral buses: General.
E8PA30/AD14Digital_IOSignal terminal PA30/AD14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA30/AD14. Supported peripheral buses: General.
E9PC10Digital_IOSignal terminal PC10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
E10PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
F1PA18/PGMD6/AD1Digital_IOSignal terminal PA18/PGMD6/AD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA18/PGMD6/AD1. Supported peripheral buses: General.
F2PC26Digital_IOSignal terminal PC26 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC26. Supported peripheral buses: General.
F3VDDOUTPower_InPrimary positive power supply input (VDDOUT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
F4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
F5VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
F6PA27/PGMD15Digital_IOSignal terminal PA27/PGMD15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA27/PGMD15. Supported peripheral buses: General.
F7PC8Digital_IOSignal terminal PC8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F8PA28Digital_IOSignal terminal PA28 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA28. Supported peripheral buses: General.
F9TSTDigital_IOSignal terminal TST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TST. Supported peripheral buses: General.
F10PC9Digital_IOSignal terminal PC9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
G1PA21/PGMD9/AD8Digital_IOSignal terminal PA21/PGMD9/AD8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA21/PGMD9/AD8. Supported peripheral buses: General.
G2PC27Digital_IOSignal terminal PC27 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC27. Supported peripheral buses: General.
G3PA15/PGMD3Digital_IOSignal terminal PA15/PGMD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA15/PGMD3. Supported peripheral buses: General.
G4VDDCOREPower_InPrimary positive power supply input (VDDCORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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