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STM32F103ZCT7 (LQFP-144(20x20)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F103ZCT7

STID: C1339990LQFP-144(20x20) · 144 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F103ZCT7 (LQFP-144(20x20))1PE22PE33PE44PE55PE66VBAT7PC13TAMPER -8PC14 - OSC329PC15 - OSC3210PF011PF112PF213PF314PF415PF516VSS_517VDD_518PF619PF720PF821PF922PF1023OSC_IN24OSC_OUT25NRST26PC027PC128PC229PC330VSSA31VREF-32VREF+33VDDA34PA0WKUP -35PA136PA237PA338VSS_439VDD_440PA441PA542PA643PA744PC445PC546PB047PB148PB249PF1150PF1251VSS_652VDD_653PF1354PF1455PF1556PG057PG158PE759PE860PE961VSS_762VDD_763PE1064PE1165PE1266PE1367PE1468PE1569PB1070PB1171VSS_172VDD_1144VDD_3143VSS_3142PE1141PE0140PB9139PB8138BOOT0137PB7136PB6135PB5134PB4133PB3132PG15131VDD_11130VSS_11129PG14128PG13127PG12126PG11125PG10124PG9123PD7122PD6121VDD_10120VSS_10119PD5118PD4117PD3116PD2115PD1114PD0113PC12112PC11111PC10110PA15109PA14108VDD_2107VSS_2106Notconnected105PA13104PA12103PA11102PA10101PA9100PA899PC998PC897PC796PC695VDD_994VSS_993PG892PG791PG690PG589PG488PG387PG286PD1585PD1484VDD_883VSS_882PD1381PD1280PD1179PD1078PD977PD876PB1575PB1474PB1373PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.896.591.486.481.376.271.166.061.055.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9-61.0-66.0-71.1-76.2-81.3-86.4-91.4-96.5mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144E=20.00mm · Pitch e=0.50mmD=20.00mm-17-15-13-11-9-7-5-3-113579111315171715131197531-1-3-5-7-9-11-13-15-17mm
3. 3D CAD MODEL
Package Body: 20.00mm × 20.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (144/144)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
4PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
5PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
6VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
7PC13TAMPER - - RTCI/OMultiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)
8PC14 - OSC32 IN(5)_I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32 IN(5)_ (RTC/CLK)
9PC15 - OSC32 OUT(5)_I/OMultiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(5)_ (RTC/CLK)
10PF0I/OMultiplexed I/O & Peripheral Pin PF0 (General)
11PF1I/OMultiplexed I/O & Peripheral Pin PF1 (General)
12PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
13PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
14PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
15PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
16VSS_5GNDGround Reference Pin (VSS_5)
17VDD_5PowerPower Supply Input (VDD_5 — 3.3V VDD (Max 4.0V))
18PF6I/OMultiplexed I/O & Peripheral Pin PF6 (ADC)
19PF7I/OMultiplexed I/O & Peripheral Pin PF7 (ADC)
20PF8I/OMultiplexed I/O & Peripheral Pin PF8 (ADC)
21PF9I/OMultiplexed I/O & Peripheral Pin PF9 (ADC)
22PF10I/OMultiplexed I/O & Peripheral Pin PF10 (ADC)
23OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
24OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
25NRSTISystem Enable & Hardware Reset (NRST)
26PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
27PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
28PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
29PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
30VSSAGNDGround Reference Pin (VSSA)
31VREF-AnalogMultiplexed I/O & Peripheral Pin VREF- (General)
32VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
33VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
34PA0WKUP -I/OMultiplexed I/O & Peripheral Pin PA0WKUP - (UART, ADC, PWM)
35PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
36PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
37PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, PWM)
38VSS_4GNDGround Reference Pin (VSS_4)
39VDD_4PowerPower Supply Input (VDD_4 — 3.3V VDD (Max 4.0V))
40PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC, DAC)
41PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, DAC)
42PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
43PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
44PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
45PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
46PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
47PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
48PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
49PF11I/OMultiplexed I/O & Peripheral Pin PF11 (General)
50PF12I/OMultiplexed I/O & Peripheral Pin PF12 (General)
51VSS_6GNDGround Reference Pin (VSS_6)
52VDD_6PowerPower Supply Input (VDD_6 — 3.3V VDD (Max 4.0V))
53PF13I/OMultiplexed I/O & Peripheral Pin PF13 (General)
54PF14I/OMultiplexed I/O & Peripheral Pin PF14 (General)
55PF15I/OMultiplexed I/O & Peripheral Pin PF15 (General)
56PG0I/OMultiplexed I/O & Peripheral Pin PG0 (General)
57PG1I/OMultiplexed I/O & Peripheral Pin PG1 (General)
58PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
59PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
60PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
61VSS_7GNDGround Reference Pin (VSS_7)
62VDD_7PowerPower Supply Input (VDD_7 — 3.3V VDD (Max 4.0V))
63PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
64PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
65PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
66PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
67PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
68PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
69PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
70PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
71VSS_1GNDGround Reference Pin (VSS_1)
72VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
73PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
74PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
75PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
76PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI)
77PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
78PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
79PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
80PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
81PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
82PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
83VSS_8GNDGround Reference Pin (VSS_8)
84VDD_8PowerPower Supply Input (VDD_8 — 3.3V VDD (Max 4.0V))
85PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
86PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
87PG2I/OMultiplexed I/O & Peripheral Pin PG2 (General)
88PG3I/OMultiplexed I/O & Peripheral Pin PG3 (General)
89PG4I/OMultiplexed I/O & Peripheral Pin PG4 (General)
90PG5I/OMultiplexed I/O & Peripheral Pin PG5 (General)
91PG6I/OMultiplexed I/O & Peripheral Pin PG6 (General)
92PG7I/OMultiplexed I/O & Peripheral Pin PG7 (General)
93PG8I/OMultiplexed I/O & Peripheral Pin PG8 (General)
94VSS_9GNDGround Reference Pin (VSS_9)
95VDD_9PowerPower Supply Input (VDD_9 — 3.3V VDD (Max 4.0V))
96PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
97PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
98PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
99PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
100PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
101PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART)
102PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
103PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, CAN)
104PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
105PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
106NotconnectedI/OMultiplexed I/O & Peripheral Pin Notconnected (General)
107VSS_2GNDGround Reference Pin (VSS_2)
108VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
109PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
110PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SPI, SWD/JTAG)
111PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART)
112PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART)
113PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART)
114PD0I/OMultiplexed I/O & Peripheral Pin PD0 (RTC/CLK)
115PD1I/OMultiplexed I/O & Peripheral Pin PD1 (RTC/CLK)
116PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
117PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
118PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
119PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
120VSS_10GNDGround Reference Pin (VSS_10)
121VDD_10PowerPower Supply Input (VDD_10 — 3.3V VDD (Max 4.0V))
122PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
123PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
124PG9I/OMultiplexed I/O & Peripheral Pin PG9 (General)
125PG10I/OMultiplexed I/O & Peripheral Pin PG10 (General)
126PG11I/OMultiplexed I/O & Peripheral Pin PG11 (General)
127PG12I/OMultiplexed I/O & Peripheral Pin PG12 (General)
128PG13I/OMultiplexed I/O & Peripheral Pin PG13 (General)
129PG14I/OMultiplexed I/O & Peripheral Pin PG14 (General)
130VSS_11GNDGround Reference Pin (VSS_11)
131VDD_11PowerPower Supply Input (VDD_11 — 3.3V VDD (Max 4.0V))
132PG15I/OMultiplexed I/O & Peripheral Pin PG15 (General)
133PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, SWD/JTAG)
134PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)
135PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
136PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
137PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
138BOOT0IInput-Only Pin BOOT0 (General)
139PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
140PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
141PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
142PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
143VSS_3GNDGround Reference Pin (VSS_3)
144VDD_3PowerPower Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
PIN 1 PE2
I/O
Multiplexed I/O & Peripheral Pin PE2 (General)
Design note: PE2 | Alt: TRACECK/FSMC_A23
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F103ZCT7 (ST · LQFP-144(20x20))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F103ZCT7 (LQFP-144(20x20)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F103ZCT7 (LQFP-144(20x20)) - 2. Standard Pinout (Top View)
True package pinout (144 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F103ZCT7 (LQFP-144(20x20)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F103ZCT7 (LQFP-144(20x20)) - 4. Package Dimensions (D×E×A)
LQFP-144(20x20) · 20.00×20.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F103ZCT7 (LQFP-144(20x20)) - 5. Recommended Land Pattern
IPC-7351B Footprint (144 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F103ZCT7 (LQFP-144(20x20)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for STM32F103
P122 · p122_fig01EXACT PACKAGE
STM32F103ZCT7 (LQFP-144(20x20)) — Figure 70. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( &
Figure 70. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( &
P124 · p124_fig01EXACT PACKAGE
STM32F103ZCT7 (LQFP-144(20x20)) — Figure 71. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
Figure 71. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
P1 · p01_fig01881×446px
STM32F103ZCT7 (LQFP-144(20x20)) — High-density performance line Arm®-based 32-bit MCU with 256 to 512KB
High-density performance line Arm®-based 32-bit MCU with 256 to 512KB
P60 · p60_fig011546×483px
STM32F103ZCT7 (LQFP-144(20x20)) — Figure 22. Typical application with an 8 MHz crystal
Figure 22. Typical application with an 8 MHz crystal
P60 · p60_fig01P60
STM32F103ZCT7 (LQFP-144(20x20)) — Datasheet Page 60 (p60_fig01)
Datasheet Page 60 (p60_fig01)
P122 · p122_fig01P122
STM32F103ZCT7 (LQFP-144(20x20)) — Datasheet Page 122 (p122_fig01)
Datasheet Page 122 (p122_fig01)
P124 · p124_fig01P124
STM32F103ZCT7 (LQFP-144(20x20)) — Datasheet Page 124 (p124_fig01)
Datasheet Page 124 (p124_fig01)
P141 · p141_fig011546×2187px
STM32F103ZCT7 (LQFP-144(20x20)) — STM32F103xC, STM32F103xD, STM32F103xE Revision history
STM32F103xC, STM32F103xD, STM32F103xE Revision history

Technical Specifications & Part Details (STM32F103ZCT7)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F103ZCT7 (LQFP-144(20x20)) is a 144-pin embedded microcontroller unit (mcu) featuring a 20.00 × 20.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
72 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
20.00 × 20.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-144(20x20))
Pin Count & Lead PitchN / e
144 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol144 auto-grouped pins
OK
IPC-7351B Land Pattern144 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-144(20x20))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
20.00 × 20.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.27 × 1.30 mm
Pins / Total PadsTopology
144P / 144Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2, C3
BOM
3× 100nF (0.1µF) 50V X7R
0402 / 0603
Digital supply decoupling caps for VDD_1..3 (Pins 24, 36, 48) — place < 1.5mm from each VDD pin.
C4
BOM
4.7µF ~ 10µF 10V X5R
0603 / 0805
Bulk decoupling capacitor for main VDD rail — place near 3.3V power entry to the MCU.
C5, C6 + FB1
BOM
100nF + 1µF + Ferrite 600Ω@100MHz
0402 / 0603
Analog rail filter for VDDA/VSSA (Pins 8, 9) 12-bit ADC — isolate digital switching noise.
Y1 + C7, C8
BOM
8MHz Crystal (CL=12pF) + 2× 18pF NP0
SMD-3225 + 0402
Main HSE oscillator crystal (Pin 5 PD0, Pin 6 PD1) — route matched traces < 4mm with GND guard ring.
STM32F103CBT6
STMicroelectronics
100% Drop-in100% Drop-in (128KB Flash Upgrade) — identical LQFP-48 pinout with doubled Flash capacity.
GD32F103C8T6
GigaDevice
Pin-to-Pin LQFP-48 (108MHz)Pin-to-Pin LQFP-48 (108MHz) — higher core clock; verify Flash wait-states & USB timing.
APM32F103C8T6
Geehy
Pin-to-Pin LQFP-48 (96MHz)Pin-to-Pin LQFP-48 (96MHz) — direct hardware replacement, register-compatible with STM32F1.

Technical Frequently Asked Questions (FAQ) — STM32F103ZCT7 (LQFP-144(20x20))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F103ZCT7 (LQFP-144(20x20))?

Manufactured by ST, the STM32F103ZCT7 is housed in a LQFP-144(20x20) package with 144 pins and a 0.50 mm lead pitch. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (General)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), 5 (PE6: Multiplexed I/O & Peripheral Pin PE6 (General)), 6 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))).

What are the IPC-7351B PCB Footprint dimensions for STM32F103ZCT7?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103ZCT7 (LQFP-144(20x20)) has a nominal body envelope of 20.00 × 20.00 mm, pitch e = 0.50 mm, and 144 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103ZCT7?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103ZCT7 (ST, LQFP-144(20x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (144 pins) & STM32F103 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
4PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
5PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
6VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
7PC13TAMPER - - RTCDigital_IOSignal terminal PC13TAMPER - - RTC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13TAMPER - - RTC. Supported peripheral buses: RTC/CLK.
8PC14 - OSC32 IN(5)_Digital_IOSignal terminal PC14 - OSC32 IN(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14 - OSC32 IN(5)_. Supported peripheral buses: RTC/CLK.
9PC15 - OSC32 OUT(5)_Digital_IOSignal terminal PC15 - OSC32 OUT(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32 OUT(5)_. Supported peripheral buses: RTC/CLK.
10PF0Digital_IOSignal terminal PF0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: General.
11PF1Digital_IOSignal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
12PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
13PF3Digital_IOSignal terminal PF3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
14PF4Digital_IOSignal terminal PF4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
15PF5Digital_IOSignal terminal PF5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
16VSS_5GND0V electrical ground return terminal (VSS_5) for internal core logic, I/O drivers, and analog sub-blocks.
17VDD_5Power_InPrimary positive power supply input (VDD_5) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
18PF6Digital_IOSignal terminal PF6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF6. Supported peripheral buses: ADC.
19PF7Digital_IOSignal terminal PF7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF7. Supported peripheral buses: ADC.
20PF8Digital_IOSignal terminal PF8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF8. Supported peripheral buses: ADC.
21PF9Digital_IOSignal terminal PF9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF9. Supported peripheral buses: ADC.
22PF10Digital_IOSignal terminal PF10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF10. Supported peripheral buses: ADC.
23OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
24OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
25NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
26PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
27PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
28PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
29PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
30VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
31VREF-AnalogSignal terminal VREF- (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF-. Supported peripheral buses: General.
32VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
33VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
34PA0WKUP -Digital_IOSignal terminal PA0WKUP - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0WKUP -. Supported peripheral buses: UART, ADC, PWM.
35PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC.
36PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
37PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, PWM.
38VSS_4GND0V electrical ground return terminal (VSS_4) for internal core logic, I/O drivers, and analog sub-blocks.
39VDD_4Power_InPrimary positive power supply input (VDD_4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
40PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, ADC, DAC.
41PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, DAC.
42PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC.
43PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC.
44PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
45PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
46PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
47PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
48PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
49PF11Digital_IOSignal terminal PF11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF11. Supported peripheral buses: General.
50PF12Digital_IOSignal terminal PF12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF12. Supported peripheral buses: General.
51VSS_6GND0V electrical ground return terminal (VSS_6) for internal core logic, I/O drivers, and analog sub-blocks.
52VDD_6Power_InPrimary positive power supply input (VDD_6) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
53PF13Digital_IOSignal terminal PF13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF13. Supported peripheral buses: General.
54PF14Digital_IOSignal terminal PF14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF14. Supported peripheral buses: General.
55PF15Digital_IOSignal terminal PF15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF15. Supported peripheral buses: General.
56PG0Digital_IOSignal terminal PG0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG0. Supported peripheral buses: General.
57PG1Digital_IOSignal terminal PG1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG1. Supported peripheral buses: General.
58PE7Digital_IOSignal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
59PE8Digital_IOSignal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: General.
60PE9Digital_IOSignal terminal PE9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: General.
61VSS_7GND0V electrical ground return terminal (VSS_7) for internal core logic, I/O drivers, and analog sub-blocks.
62VDD_7Power_InPrimary positive power supply input (VDD_7) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
63PE10Digital_IOSignal terminal PE10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: General.
64PE11Digital_IOSignal terminal PE11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: General.
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