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STM32F205RGY6TR (VFBGA-64) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F205RGY6TR

STID: C1339629VFBGA-64 · 66 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F205RGY6TR (VFBGA-64)A1PA14A2PA15A3PC12A4PB3A5PB5A6PB7A7PB9A8VDDA9VBATB1VSSB2PA13B3PC10B4PB4B5PB6B6BOOT0B7PB8B8PC13B9PC14C1PA12C2VCAP_2C3PC11C7PD2C8IRROFFC9PC15D1PC9D2PA11D3PA10D7PC2D8VSSD9VDDE1VDDE2PA8E3PA9J9PA2J8PA4J7PA7J6PB0J5PB1J4PB2J3VCAP_1J2PB11J1PB12H9VSS_5H8PA1H7REGOFFH6PA5H5PA6H4PC4H3PB10H2PB13H1PB14G9PC0G8PC3G7PA3G3PC5G2PC6G1PB15F9PH1-OSC_OUTF8PC1F7VREF+F3PC8F2PC7F1VSSE9PH0-OSC_INE8NRSTE7PA0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.848.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1A2B2C2D2E2F2G2H2J2A3B3C3D3E3F3G3H3J3A4B4H4J4A5B5H5J5A6B6H6J6A7B7C7D7E7F7G7H7J7A8B8C8D8E8F8G8H8J8A9B9C9D9E9F9G9H9J9E=3.60mm · Pitch e=0.40mmD=3.90mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.60mm × 3.90mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (66/66)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
A2PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
A3PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
A4PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
A5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
A6PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
A7PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
A8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A9VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B1VSSGNDGround Reference Pin (VSS)
B2PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
B3PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
B4PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
B6BOOT0IInput-Only Pin BOOT0 (General)
B7PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
B8PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
B9PC14I/OMultiplexed I/O & Peripheral Pin PC14 (General)
C1PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
C2VCAP_2I/OMultiplexed I/O & Peripheral Pin VCAP_2 (General)
C3PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
C7PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
C8IRROFFI/OMultiplexed I/O & Peripheral Pin IRROFF (General)
C9PC15I/OMultiplexed I/O & Peripheral Pin PC15 (General)
D1PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
D2PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
D3PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
D7PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
D8VSSGNDGround Reference Pin (VSS)
D9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E2PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
E3PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
E7PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
E8NRSTISystem Enable & Hardware Reset (NRST)
E9PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
F1VSSGNDGround Reference Pin (VSS)
F2PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
F3PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F7VREF+I/OMultiplexed I/O & Peripheral Pin VREF+ (General)
F8PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
F9PH1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)
G1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
G2PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
G3PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
G7PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
G8PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
G9PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
H1PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
H2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
H3PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
H4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
H5PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
H6PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
H7REGOFFI/OMultiplexed I/O & Peripheral Pin REGOFF (General)
H8PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
H9VSS_5GNDGround Reference Pin (VSS_5)
J1PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
J2PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
J3VCAP_1I/OMultiplexed I/O & Peripheral Pin VCAP_1 (General)
J4PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
J5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
J6PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
J7PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
J8PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
J9PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
PIN A1 PA14
I/O
Multiplexed I/O & Peripheral Pin PA14 (General)
Design note: Signal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F205RGY6TR (ST · VFBGA-64)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F205RGY6TR (VFBGA-64) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F205RGY6TR (VFBGA-64) - 2. Standard Pinout (Top View)
True package pinout (66 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F205RGY6TR (VFBGA-64) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F205RGY6TR (VFBGA-64) - 4. Package Dimensions (D×E×A)
VFBGA-64 · 3.60×3.90mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F205RGY6TR (VFBGA-64) - 5. Recommended Land Pattern
IPC-7351B Footprint (66 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F205RGY6TR (VFBGA-64) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for STM32F207 / STM32F205
P148 · p148_fig01EXACT PACKAGE
STM32F205RGY6TR (VFBGA-64) — Figure 77. LQFP64 outline
Figure 77. LQFP64 outline
P1 · p01_fig01881×566px
STM32F205RGY6TR (VFBGA-64) —   Up to 140 I/O ports with interrupt capability: - Up to 136 fast I/Os up to 60 MHz - Up to 138 5 V-tolerant I/Os
  Up to 140 I/O ports with interrupt capability: - Up to 136 fast I/Os up to 60 MHz - Up to 138 5 V-tolerant I/Os
P41 · p41_fig011546×1008px
STM32F205RGY6TR (VFBGA-64) — Figure 10. STM32F20x LQFP64 pinout
Figure 10. STM32F20x LQFP64 pinout
P41 · p41_fig021546×1321px
STM32F205RGY6TR (VFBGA-64) — Figure 11. STM32F20x WLCSP64+2 ballout 1 2 3 8
Figure 11. STM32F20x WLCSP64+2 ballout 1 2 3 8
P42 · p42_fig011546×1466px
STM32F205RGY6TR (VFBGA-64) — Figure 12. STM32F20x LQFP100 pinout
Figure 12. STM32F20x LQFP100 pinout
P42 · p42_fig01P42
STM32F205RGY6TR (VFBGA-64) — Datasheet Page 42 (p42_fig01)
Datasheet Page 42 (p42_fig01)
P68 · p68_fig011751×1623px
STM32F205RGY6TR (VFBGA-64) — Figure 19. Power supply scheme VBAT
Figure 19. Power supply scheme VBAT
P68 · p68_fig01P68
STM32F205RGY6TR (VFBGA-64) — Datasheet Page 68 (p68_fig01)
Datasheet Page 68 (p68_fig01)
P90 · p90_fig011546×484px
STM32F205RGY6TR (VFBGA-64) — Figure 32. Typical application with an 8 MHz crystal
Figure 32. Typical application with an 8 MHz crystal
P91 · p91_fig011751×593px
STM32F205RGY6TR (VFBGA-64) — Figure 33. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors
Figure 33. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors
P149 · p149_fig011546×1060px
STM32F205RGY6TR (VFBGA-64) — Figure 78. LQFP64 recommended footprint
Figure 78. LQFP64 recommended footprint
P149 · p149_fig01P149
STM32F205RGY6TR (VFBGA-64) — Datasheet Page 149 (p149_fig01)
Datasheet Page 149 (p149_fig01)
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (STM32F205RGY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F205RGY6TR (VFBGA-64) is a 64-pin embedded microcontroller unit (mcu) featuring a 3.90 × 3.60 × 0.55 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SPI, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
120 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.90 × 3.60 × 0.55 mm (A1=0.18 mm)
Package family: WLCSP (VFBGA-64)
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, I2C, I2S, ADC, PWM, SDIO, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, SPI, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol66 auto-grouped pins
OK
IPC-7351B Land Pattern66 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VFBGA-64)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.90 × 3.60 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.22 mm
Pins / Total PadsTopology
66P / 66Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
VFBGA-64
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F205RGY6TR (VFBGA-64)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F205RGY6TR (VFBGA-64)?

Manufactured by ST, the STM32F205RGY6TR is housed in a VFBGA-64 package with 66 pins and a 0.40 mm lead pitch. Key pins include: A1 (PA14: Multiplexed I/O & Peripheral Pin PA14 (General)), A2 (PA15: Multiplexed I/O & Peripheral Pin PA15 (General)), A3 (PC12: Multiplexed I/O & Peripheral Pin PC12 (General)), A4 (PB3: Multiplexed I/O & Peripheral Pin PB3 (General)), A5 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)), A6 (PB7: Multiplexed I/O & Peripheral Pin PB7 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32F205RGY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F205RGY6TR (VFBGA-64) has a nominal body envelope of 3.60 × 3.90 mm, pitch e = 0.40 mm, and 66 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F205RGY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F205RGY6TR (ST, VFBGA-64) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (66 pins) & STM32F207 / STM32F205 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
A2PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
A3PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
A4PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
A5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
A6PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
A7PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
A8VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A9VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B2PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
B3PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
B4PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
B6BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
B7PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
B8PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
B9PC14Digital_IOSignal terminal PC14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14. Supported peripheral buses: General.
C1PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
C2VCAP_2Digital_IOSignal terminal VCAP_2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_2. Supported peripheral buses: General.
C3PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
C7PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
C8IRROFFDigital_IOSignal terminal IRROFF (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: IRROFF. Supported peripheral buses: General.
C9PC15Digital_IOSignal terminal PC15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15. Supported peripheral buses: General.
D1PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
D2PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
D3PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
D7PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
D8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E2PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
E3PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
E7PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
E8NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E9PH0-OSC_INDigital_IOSignal terminal PH0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK.
F1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F2PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
F3PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F7VREF+Digital_IOSignal terminal VREF+ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
F8PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
F9PH1-OSC_OUTDigital_IOSignal terminal PH1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1-OSC_OUT. Supported peripheral buses: RTC/CLK.
G1PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
G2PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
G3PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
G7PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
G8PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
G9PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
H1PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
H2PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
H3PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
H4PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
H5PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
H6PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
H7REGOFFDigital_IOSignal terminal REGOFF (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: REGOFF. Supported peripheral buses: General.
H8PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
H9VSS_5GND0V electrical ground return terminal (VSS_5) for internal core logic, I/O drivers, and analog sub-blocks.
J1PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
J2PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
J3VCAP_1Digital_IOSignal terminal VCAP_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_1. Supported peripheral buses: General.
J4PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
J5PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
J6PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
J7PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
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