![STM32L063C8T6 (LQFP-48(7x7)) — Figure 3. STM32L063x8 LQFP64 pinout VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 [LQFP-64(10x10)]](/api/v1/assets/C1338372/extracted/figures/p37_fig01.png)
LQFP-48(7x7) · 48P
Synchronized Pinout (Symbol / 2D / 3D) (48/48)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | VLCD | I/O | Multiplexed I/O & Peripheral Pin VLCD (General) |
| 2 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| 3 | 3V3 | Power | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | NC | NC | No Connect (Leave Floating) |
| 5 | PH0OSC IN(PH0) -_ | I/O | Multiplexed I/O & Peripheral Pin PH0OSC IN(PH0) -_ (USB, RTC/CLK) |
| 6 | PH1OSC OUT(PH1) -_ | I/O | Multiplexed I/O & Peripheral Pin PH1OSC OUT(PH1) -_ (RTC/CLK) |
| 7 | NRST | I | System Enable & Hardware Reset (NRST) |
| 8 | VSSA | GND | Ground Reference Pin (VSSA) |
| 9 | VDDA | Power | Power Supply Input (VDDA — 3.3V VDD (Max 4.0V)) |
| 10 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (UART, PWM, RTC/CLK) |
| 11 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART) |
| 12 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (UART) |
| 13 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (UART) |
| 14 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, DAC) |
| 15 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (SPI, PWM) |
| 16 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC) |
| 17 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC) |
| 18 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (General) |
| 19 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (UART, ADC) |
| 20 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (General) |
| 21 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (SPI, PWM) |
| 22 | PB11 | I/O | Multiplexed I/O & Peripheral Pin PB11 (I2C, PWM) |
| 23 | VSS | GND | Ground Reference Pin (VSS) |
| 24 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 25 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C) |
| 26 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (UART, SPI, I2C) |
| 27 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (UART, SPI, I2C, RTC/CLK) |
| 28 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (SPI, RTC/CLK) |
| 29 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (USB, UART, RTC/CLK) |
| 30 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (UART, RTC/CLK) |
| 31 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (UART) |
| 32 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI) |
| 33 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI) |
| 34 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (USB, SWD/JTAG) |
| 35 | VSS | GND | Ground Reference Pin (VSS) |
| 36 | VDD_USB | Power | Power Supply Input (VDD_USB — 3.3V VDD (Max 4.0V)) |
| 37 | PA14 | I/O | Multiplexed I/O & Peripheral Pin PA14 (UART, SWD/JTAG) |
| 38 | PA15 | I/O | Multiplexed I/O & Peripheral Pin PA15 (UART, SPI, PWM) |
| 39 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (SPI, PWM) |
| 40 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (SPI) |
| 41 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C) |
| 42 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (UART, I2C) |
| 43 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (UART, I2C) |
| 44 | BOOT0 | I | Input-Only Pin BOOT0 (General) |
| 45 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (General) |
| 46 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (General) |
| 47 | VSS | GND | Ground Reference Pin (VSS) |
| 48 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
PIN 1 VLCD
I/OMultiplexed I/O & Peripheral Pin VLCD (General)
Design note: Signal terminal VLCD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLCD. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for STM32L063
P1 · p01_fig01EXACT PACKAGE
P38 · p38_fig01EXACT PACKAGE
P115 · p115_fig01EXACT PACKAGE
P116 · p116_fig01EXACT PACKAGE
P38 · p38_fig021546×1007px
P52 · p52_fig011546×1527px
P53 · p53_fig011546×975px
P53 · p53_fig021546×555px
P94 · p94_fig011751×902px
P94 · p94_fig021546×705px
P119 · p119_fig011546×1055px
P37 · p37_fig01EXACT PACKAGE
Page 1 / 2 (14 extracted figures)
Technical Specifications & Part Details (STM32L063C8T6)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32L063C8T6 (LQFP-48(7x7)) is a 48-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.65 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.65 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
30 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol48 auto-grouped pins
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32L063 (4)
LQFP-64(10x10) · 64P
LQFP-64(10x10) · 64P
LQFP-64(10x10) · 64P
Mechanical Dimensions & Land Pattern (LQFP-48(7x7))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.20 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-48(7x7) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32L063C8T6 (LQFP-48(7x7))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32L063C8T6 (LQFP-48(7x7))?
Manufactured by ST, the STM32L063C8T6 is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: 1 (VLCD: Multiplexed I/O & Peripheral Pin VLCD (General)), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (3V3: 3.3V Main Power Supply Rail (3.0V ~ 3.6V)), 4 (NC: No Connect (Leave Floating)), 5 (PH0OSC IN(PH0) -_: Multiplexed I/O & Peripheral Pin PH0OSC IN(PH0) -_ (USB, RTC/CLK)), 6 (PH1OSC OUT(PH1) -_: Multiplexed I/O & Peripheral Pin PH1OSC OUT(PH1) -_ (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for STM32L063C8T6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L063C8T6 (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L063C8T6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L063C8T6 (ST, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (48 pins) & STM32L063 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VLCD | Digital_IO | Signal terminal VLCD (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLCD. Supported peripheral buses: General. |
| 2 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| 3 | 3V3 | Power_In | 3.3V Main Power Supply Rail (3.0V ~ 3.6V) |
| 4 | NC | No_Connect | No Connect (Leave Floating) |
| 5 | PH0OSC IN(PH0) -_ | Digital_IO | Signal terminal PH0OSC IN(PH0) -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0OSC IN(PH0) -_. Supported peripheral buses: USB, RTC/CLK. |
| 6 | PH1OSC OUT(PH1) -_ | Digital_IO | Signal terminal PH1OSC OUT(PH1) -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1OSC OUT(PH1) -_. Supported peripheral buses: RTC/CLK. |
| 7 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 8 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 10 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, PWM, RTC/CLK. |
| 11 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART. |
| 12 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART. |
| 13 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART. |
| 14 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, DAC. |
| 15 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCKTIM2ETR. Supported peripheral buses: SPI, PWM. |
| 16 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC. |
| 17 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC. |
| 18 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General. |
| 19 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC. |
| 20 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General. |
| 21 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCKI2C2SCL. Supported peripheral buses: SPI, PWM. |
| 22 | PB11 | Digital_IO | Signal terminal PB11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: I2C, PWM. |
| 23 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 24 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 25 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA. Supported peripheral buses: UART, SPI, I2C. |
| 26 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, I2C. |
| 27 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, I2C, RTC/CLK. |
| 28 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, RTC/CLK. |
| 29 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: USB, UART, RTC/CLK. |
| 30 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, RTC/CLK. |
| 31 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART. |
| 32 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO, USB_DM. Supported peripheral buses: USB, UART, SPI. |
| 33 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, USB_DP. Supported peripheral buses: USB, UART, SPI. |
| 34 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: USB, SWD/JTAG. |
| 35 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 36 | VDD_USB | Power_In | Primary positive power supply input (VDD_USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 37 | PA14 | Digital_IO | Signal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: UART, SWD/JTAG. |
| 38 | PA15 | Digital_IO | Signal terminal PA15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, PWM. |
| 39 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCKLCDSEG7. Supported peripheral buses: SPI, PWM. |
| 40 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI. |
| 41 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C1_SMBA. Supported peripheral buses: SPI, I2C. |
| 42 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C. |
| 43 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART, I2C. |
| 44 | BOOT0 | Digital_IO | Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General. |
| 45 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General. |
| 46 | PB9 | Digital_IO | Signal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General. |
| 47 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 48 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |