STM32F103ZGH6 (LFBGA-144) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of STM32F103ZGH6 (LFBGA-144)?

Manufactured by ST, the STM32F103ZGH6 is housed in a LFBGA-144 package with 144 pins and a 0.80 mm lead pitch. Key pins include: A1 (PC13TAMPER - - RTC: Multiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)), A2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), A3 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), A4 (PE1: Multiplexed I/O & Peripheral Pin PE1 (General)), A5 (PE0: Multiplexed I/O & Peripheral Pin PE0 (General)), A6 (PB4: Multiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)).

Q: What are the IPC-7351B PCB Footprint dimensions for STM32F103ZGH6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103ZGH6 (LFBGA-144) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 144 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103ZGH6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103ZGH6 (ST, LFBGA-144) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (144/144)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
A1	PC13TAMPER - - RTC	I/O	Multiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)
A2	PE3	I/O	Multiplexed I/O & Peripheral Pin PE3 (General)
A3	PE2	I/O	Multiplexed I/O & Peripheral Pin PE2 (General)
A4	PE1	I/O	Multiplexed I/O & Peripheral Pin PE1 (General)
A5	PE0	I/O	Multiplexed I/O & Peripheral Pin PE0 (General)
A6	PB4	I/O	Multiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)
A7	PB3	I/O	Multiplexed I/O & Peripheral Pin PB3 (SPI, SWD/JTAG)
A8	PD6	I/O	Multiplexed I/O & Peripheral Pin PD6 (General)
A9	PD7	I/O	Multiplexed I/O & Peripheral Pin PD7 (General)
A10	PA15	I/O	Multiplexed I/O & Peripheral Pin PA15 (SPI, SWD/JTAG)
A11	PA14	I/O	Multiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
A12	PA13	I/O	Multiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
B1	PC14OSC32 IN(5) -_	I/O	Multiplexed I/O & Peripheral Pin PC14OSC32 IN(5) -_ (RTC/CLK)
B2	PE4	I/O	Multiplexed I/O & Peripheral Pin PE4 (General)
B3	PE5	I/O	Multiplexed I/O & Peripheral Pin PE5 (General)
B4	PE6	I/O	Multiplexed I/O & Peripheral Pin PE6 (General)
B5	PB9	I/O	Multiplexed I/O & Peripheral Pin PB9 (General)
B6	PB5	I/O	Multiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
B7	PG15	I/O	Multiplexed I/O & Peripheral Pin PG15 (General)
B8	PG12	I/O	Multiplexed I/O & Peripheral Pin PG12 (General)
B9	PD5	I/O	Multiplexed I/O & Peripheral Pin PD5 (General)
B10	PC11	I/O	Multiplexed I/O & Peripheral Pin PC11 (UART)
B11	PC10	I/O	Multiplexed I/O & Peripheral Pin PC10 (UART)
B12	PA12	I/O	Multiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
C1	PC15 - OSC32 OUT(5)_	I/O	Multiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(5)_ (RTC/CLK)
C2	VBAT	Power	Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C3	PF0	I/O	Multiplexed I/O & Peripheral Pin PF0 (General)
C4	PF1	I/O	Multiplexed I/O & Peripheral Pin PF1 (General)
C5	PB8	I/O	Multiplexed I/O & Peripheral Pin PB8 (General)
C6	PB6	I/O	Multiplexed I/O & Peripheral Pin PB6 (I2C)
C7	PG14	I/O	Multiplexed I/O & Peripheral Pin PG14 (General)
C8	PG11	I/O	Multiplexed I/O & Peripheral Pin PG11 (General)
C9	PD4	I/O	Multiplexed I/O & Peripheral Pin PD4 (General)
C10	PC12	I/O	Multiplexed I/O & Peripheral Pin PC12 (UART)
C11	Notconnected	I/O	Multiplexed I/O & Peripheral Pin Notconnected (General)
C12	PA11	I/O	Multiplexed I/O & Peripheral Pin PA11 (USB, UART, CAN)
D1	OSC_IN	I/O	Multiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
D2	VSS_5	GND	Ground Reference Pin (VSS_5)
D3	VDD_5	Power	Power Supply Input (VDD_5 — 3.3V VDD (Max 4.0V))
D4	PF2	I/O	Multiplexed I/O & Peripheral Pin PF2 (General)
D5	BOOT0	I	Input-Only Pin BOOT0 (General)
D6	PB7	I/O	Multiplexed I/O & Peripheral Pin PB7 (I2C)
D7	PG13	I/O	Multiplexed I/O & Peripheral Pin PG13 (General)
D8	PG10	I/O	Multiplexed I/O & Peripheral Pin PG10 (General)
D9	PD3	I/O	Multiplexed I/O & Peripheral Pin PD3 (General)
D10	PD1	I/O	Multiplexed I/O & Peripheral Pin PD1 (General)
D11	PA10	I/O	Multiplexed I/O & Peripheral Pin PA10 (UART)
D12	PA9	I/O	Multiplexed I/O & Peripheral Pin PA9 (UART)
E1	OSC_OUT	I/O	Multiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
E2	PF3	I/O	Multiplexed I/O & Peripheral Pin PF3 (General)
E3	PF4	I/O	Multiplexed I/O & Peripheral Pin PF4 (General)
E4	PF5	I/O	Multiplexed I/O & Peripheral Pin PF5 (General)
E5	VSS_3	GND	Ground Reference Pin (VSS_3)
E6	VSS_11	GND	Ground Reference Pin (VSS_11)
E7	VSS_10	GND	Ground Reference Pin (VSS_10)
E8	PG9	I/O	Multiplexed I/O & Peripheral Pin PG9 (General)
E9	PD2	I/O	Multiplexed I/O & Peripheral Pin PD2 (UART)
E10	PD0	I/O	Multiplexed I/O & Peripheral Pin PD0 (General)
E11	PC9	I/O	Multiplexed I/O & Peripheral Pin PC9 (General)
E12	PA8	I/O	Multiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
F1	NRST	I	System Enable & Hardware Reset (NRST)
F2	PF7	I/O	Multiplexed I/O & Peripheral Pin PF7 (ADC)
F3	PF6	I/O	Multiplexed I/O & Peripheral Pin PF6 (ADC)
F4	VDD_4	Power	Power Supply Input (VDD_4 — 3.3V VDD (Max 4.0V))
F5	VDD_3	Power	Power Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
F6	VDD_11	Power	Power Supply Input (VDD_11 — 3.3V VDD (Max 4.0V))
F7	VDD_10	Power	Power Supply Input (VDD_10 — 3.3V VDD (Max 4.0V))
F8	VDD_8	Power	Power Supply Input (VDD_8 — 3.3V VDD (Max 4.0V))
F9	VDD_2	Power	Power Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
F10	VDD_9	Power	Power Supply Input (VDD_9 — 3.3V VDD (Max 4.0V))
F11	PC8	I/O	Multiplexed I/O & Peripheral Pin PC8 (General)
F12	PC7	I/O	Multiplexed I/O & Peripheral Pin PC7 (General)
G1	PF10	I/O	Multiplexed I/O & Peripheral Pin PF10 (ADC)
G2	PF9	I/O	Multiplexed I/O & Peripheral Pin PF9 (ADC)
G3	PF8	I/O	Multiplexed I/O & Peripheral Pin PF8 (ADC)
G4	VSS_4	GND	Ground Reference Pin (VSS_4)
G5	VDD_6	Power	Power Supply Input (VDD_6 — 3.3V VDD (Max 4.0V))
G6	VDD_7	Power	Power Supply Input (VDD_7 — 3.3V VDD (Max 4.0V))
G7	VDD_1	Power	Power Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
G8	VSS_8	GND	Ground Reference Pin (VSS_8)
G9	VSS_2	GND	Ground Reference Pin (VSS_2)
G10	VSS_9	GND	Ground Reference Pin (VSS_9)
G11	PG8	I/O	Multiplexed I/O & Peripheral Pin PG8 (General)
G12	PC6	I/O	Multiplexed I/O & Peripheral Pin PC6 (General)
H1	PC0	I/O	Multiplexed I/O & Peripheral Pin PC0 (ADC)
H2	PC1	I/O	Multiplexed I/O & Peripheral Pin PC1 (ADC)
H3	PC2	I/O	Multiplexed I/O & Peripheral Pin PC2 (ADC)
H4	PC3	I/O	Multiplexed I/O & Peripheral Pin PC3 (ADC)
H5	VSS_6	GND	Ground Reference Pin (VSS_6)
H6	VSS_7	GND	Ground Reference Pin (VSS_7)
H7	VSS_1	GND	Ground Reference Pin (VSS_1)
H8	PE11	I/O	Multiplexed I/O & Peripheral Pin PE11 (General)
H9	PD11	I/O	Multiplexed I/O & Peripheral Pin PD11 (General)
H10	PG7	I/O	Multiplexed I/O & Peripheral Pin PG7 (General)
H11	PG6	I/O	Multiplexed I/O & Peripheral Pin PG6 (General)
H12	PG5	I/O	Multiplexed I/O & Peripheral Pin PG5 (General)
J1	VSSA	GND	Ground Reference Pin (VSSA)
J2	PA0WKUP -	I/O	Multiplexed I/O & Peripheral Pin PA0WKUP - (UART, ADC)
J3	PA4	I/O	Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
J4	PC4	I/O	Multiplexed I/O & Peripheral Pin PC4 (ADC)
J5	PB2	I/O	Multiplexed I/O & Peripheral Pin PB2 (General)
J6	PG1	I/O	Multiplexed I/O & Peripheral Pin PG1 (General)
J7	PE10	I/O	Multiplexed I/O & Peripheral Pin PE10 (General)
J8	PE12	I/O	Multiplexed I/O & Peripheral Pin PE12 (General)
J9	PD10	I/O	Multiplexed I/O & Peripheral Pin PD10 (General)
J10	PG4	I/O	Multiplexed I/O & Peripheral Pin PG4 (General)
J11	PG3	I/O	Multiplexed I/O & Peripheral Pin PG3 (General)
J12	PG2	I/O	Multiplexed I/O & Peripheral Pin PG2 (General)
K1	VREF-	Analog	Multiplexed I/O & Peripheral Pin VREF- (General)
K2	PA1	I/O	Multiplexed I/O & Peripheral Pin PA1 (UART, ADC)
K3	PA5	I/O	Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC)
K4	PC5	I/O	Multiplexed I/O & Peripheral Pin PC5 (ADC)
K5	PF13	I/O	Multiplexed I/O & Peripheral Pin PF13 (General)
K6	PG0	I/O	Multiplexed I/O & Peripheral Pin PG0 (General)
K7	PE9	I/O	Multiplexed I/O & Peripheral Pin PE9 (General)
K8	PE13	I/O	Multiplexed I/O & Peripheral Pin PE13 (General)
K9	PD9	I/O	Multiplexed I/O & Peripheral Pin PD9 (General)
K10	PD13	I/O	Multiplexed I/O & Peripheral Pin PD13 (General)
K11	PD14	I/O	Multiplexed I/O & Peripheral Pin PD14 (General)
K12	PD15	I/O	Multiplexed I/O & Peripheral Pin PD15 (General)
L1	VREF+	Analog	Multiplexed I/O & Peripheral Pin VREF+ (General)
L2	PA2	I/O	Multiplexed I/O & Peripheral Pin PA2 (UART, ADC)
L3	PA6	I/O	Multiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
L4	PB0	I/O	Multiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
L5	PF12	I/O	Multiplexed I/O & Peripheral Pin PF12 (General)
L6	PF15	I/O	Multiplexed I/O & Peripheral Pin PF15 (General)
L7	PE8	I/O	Multiplexed I/O & Peripheral Pin PE8 (General)
L8	PE14	I/O	Multiplexed I/O & Peripheral Pin PE14 (General)
L9	PD8	I/O	Multiplexed I/O & Peripheral Pin PD8 (General)
L10	PD12	I/O	Multiplexed I/O & Peripheral Pin PD12 (General)
L11	PB14	I/O	Multiplexed I/O & Peripheral Pin PB14 (UART, SPI)
L12	PB15	I/O	Multiplexed I/O & Peripheral Pin PB15 (SPI)
M1	VDDA	Power	Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))
M2	PA3	I/O	Multiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
M3	PA7	I/O	Multiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
M4	PB1	I/O	Multiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
M5	PF11	I/O	Multiplexed I/O & Peripheral Pin PF11 (General)
M6	PF14	I/O	Multiplexed I/O & Peripheral Pin PF14 (General)
M7	PE7	I/O	Multiplexed I/O & Peripheral Pin PE7 (General)
M8	PE15	I/O	Multiplexed I/O & Peripheral Pin PE15 (General)
M9	PB10	I/O	Multiplexed I/O & Peripheral Pin PB10 (UART, I2C)
M10	PB11	I/O	Multiplexed I/O & Peripheral Pin PB11 (UART, I2C)
M11	PB12	I/O	Multiplexed I/O & Peripheral Pin PB12 (SPI, I2C)
M12	PB13	I/O	Multiplexed I/O & Peripheral Pin PB13 (UART, SPI)

PIN A1 PC13TAMPER - - RTC

I/O

Multiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)

Design note: PC13(6) | Alt: TAMPERRTC -

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

STM32F103ZGH6 (LFBGA-144) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

STM32F103ZGH6 (LFBGA-144) - 2. Standard Pinout (Top View)

True package pinout (144 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

STM32F103ZGH6 (LFBGA-144) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

STM32F103ZGH6 (LFBGA-144) - 4. Package Dimensions (D×E×A)

LFBGA-144 · 10.00×10.00mm · Pitch 0.80mmExpand ›

5. Recommended Land PatternLAND PATTERN

STM32F103ZGH6 (LFBGA-144) - 5. Recommended Land Pattern

IPC-7351B Footprint (144 Pads)Expand ›

6. Application SchematicSCHEMATIC

STM32F103ZGH6 (LFBGA-144) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)

Showing 1–12 of 12 uncropped original figures for STM32F103

P25 · p25_fig01EXACT PACKAGE

Figure 3. STM32F103xF/G BGA144 ballout

P117 · p117_fig01EXACT PACKAGE

Figure 60. LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm,

P121 · p121_fig01EXACT PACKAGE

Figure 63. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package

P1 · p01_fig01881×450px

XL-density performance line ARM®-based 32-bit MCU with 768 KB

P1 · p01_fig02887×303px

• ECOPACK® packages

P41 · p41_fig011761×1558px

Figure 10. Power supply scheme

P41 · p41_fig01P41

Datasheet Page 41 (p41_fig01)

P111 · p111_fig011546×613px

Figure 56. Typical connection diagram using the ADC

P117 · p117_fig01P117

Datasheet Page 117 (p117_fig01)

P121 · p121_fig01P121

Datasheet Page 121 (p121_fig01)

P135 · p135_fig011546×1934px

STM32F103xF, STM32F103xG Revision history

P111 · p111_fig02All Packages in PDF

Figure 57. Power supply and reference decoupling (VREF+ not connected to VDDA)

Technical Specifications & Part Details (STM32F103ZGH6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Embedded Microcontroller Unit (MCU)

Detailed Overview:STM32F103ZGH6 (LFBGA-144) is a 144-pin embedded microcontroller unit (mcu) featuring a 10.00 × 10.00 × 1.60 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG, UART interfaces.

Operating Supply VoltageV_CC / V_DD

3.0V ~ 3.6V (Typ 3.3V)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C ~ +85°C (Industrial Grade)

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

72 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

10.00 × 10.00 × 1.60 mm (A1=0.30 mm)

Package family: BGA (LFBGA-144)

Pin Count & Lead PitchN / e

144 Pins | Pitch e = 0.80 mm (31.5 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG, UART

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2): Do not force conflicting external pull-ups/pull-downs during POR reset.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol144 auto-grouped pins

IPC-7351B Land Pattern144 pads · Pitch 0.80mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LFBGA-144)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

10.00 × 10.00 mm

Height (A) & Pitch (e)IPC-7351B

A=1.60mm · e=0.80mm

Pad Size (W × L)Level B

0.36 × 0.36 mm

Pins / Total PadsTopology

144P / 144Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
C1, C2, C3 BOM	3× 100nF (0.1µF) 50V X7R 0402 / 0603	Digital supply decoupling caps for VDD_1..3 (Pins 24, 36, 48) — place < 1.5mm from each VDD pin.
C4 BOM	4.7µF ~ 10µF 10V X5R 0603 / 0805	Bulk decoupling capacitor for main VDD rail — place near 3.3V power entry to the MCU.
C5, C6 + FB1 BOM	100nF + 1µF + Ferrite 600Ω@100MHz 0402 / 0603	Analog rail filter for VDDA/VSSA (Pins 8, 9) 12-bit ADC — isolate digital switching noise.
Y1 + C7, C8 BOM	8MHz Crystal (CL=12pF) + 2× 18pF NP0 SMD-3225 + 0402	Main HSE oscillator crystal (Pin 5 PD0, Pin 6 PD1) — route matched traces < 4mm with GND guard ring.
STM32F103CBT6 STMicroelectronics	100% Drop-in (128KB Flash Upgrade)	100% Drop-in (128KB Flash Upgrade) — identical LQFP-48 pinout with doubled Flash capacity.
GD32F103C8T6 GigaDevice	Pin-to-Pin LQFP-48 (108MHz)	Pin-to-Pin LQFP-48 (108MHz) — higher core clock; verify Flash wait-states & USB timing.
APM32F103C8T6 Geehy	Pin-to-Pin LQFP-48 (96MHz)	Pin-to-Pin LQFP-48 (96MHz) — direct hardware replacement, register-compatible with STM32F1.

Technical Frequently Asked Questions (FAQ) — STM32F103ZGH6 (LFBGA-144)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F103ZGH6 (LFBGA-144)?

Manufactured by ST, the STM32F103ZGH6 is housed in a LFBGA-144 package with 144 pins and a 0.80 mm lead pitch. Key pins include: A1 (PC13TAMPER - - RTC: Multiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)), A2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), A3 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), A4 (PE1: Multiplexed I/O & Peripheral Pin PE1 (General)), A5 (PE0: Multiplexed I/O & Peripheral Pin PE0 (General)), A6 (PB4: Multiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)).

What are the IPC-7351B PCB Footprint dimensions for STM32F103ZGH6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103ZGH6 (LFBGA-144) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 144 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103ZGH6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103ZGH6 (ST, LFBGA-144) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (144 pins) & STM32F103 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
A1	PC13TAMPER - - RTC	Digital_IO	Signal terminal PC13TAMPER - - RTC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13TAMPER - - RTC. Supported peripheral buses: RTC/CLK.
A2	PE3	Digital_IO	Signal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
A3	PE2	Digital_IO	Signal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
A4	PE1	Digital_IO	Signal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
A5	PE0	Digital_IO	Signal terminal PE0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
A6	PB4	Digital_IO	Signal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: SPI, SWD/JTAG.
A7	PB3	Digital_IO	Signal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: SPI, SWD/JTAG.
A8	PD6	Digital_IO	Signal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
A9	PD7	Digital_IO	Signal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
A10	PA15	Digital_IO	Signal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: SPI, SWD/JTAG.
A11	PA14	Digital_IO	Signal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
A12	PA13	Digital_IO	Signal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
B1	PC14OSC32 IN(5) -_	Digital_IO	Signal terminal PC14OSC32 IN(5) -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14OSC32 IN(5) -_. Supported peripheral buses: RTC/CLK.
B2	PE4	Digital_IO	Signal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
B3	PE5	Digital_IO	Signal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
B4	PE6	Digital_IO	Signal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
B5	PB9	Digital_IO	Signal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
B6	PB5	Digital_IO	Signal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBA, SPI3_MOSI. Supported peripheral buses: SPI, I2C.
B7	PG15	Digital_IO	Signal terminal PG15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG15. Supported peripheral buses: General.
B8	PG12	Digital_IO	Signal terminal PG12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG12. Supported peripheral buses: General.
B9	PD5	Digital_IO	Signal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
B10	PC11	Digital_IO	Signal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART.
B11	PC10	Digital_IO	Signal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: UART.
B12	PA12	Digital_IO	Signal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USB_DP. Supported peripheral buses: USB, UART, CAN.
C1	PC15 - OSC32 OUT(5)_	Digital_IO	Signal terminal PC15 - OSC32 OUT(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32 OUT(5)_. Supported peripheral buses: RTC/CLK.
C2	VBAT	Power_In	Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C3	PF0	Digital_IO	Signal terminal PF0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: General.
C4	PF1	Digital_IO	Signal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
C5	PB8	Digital_IO	Signal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
C6	PB6	Digital_IO	Signal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
C7	PG14	Digital_IO	Signal terminal PG14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG14. Supported peripheral buses: General.
C8	PG11	Digital_IO	Signal terminal PG11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG11. Supported peripheral buses: General.
C9	PD4	Digital_IO	Signal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
C10	PC12	Digital_IO	Signal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: UART.
C11	Notconnected	Digital_IO	Signal terminal Notconnected (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: Notconnected. Supported peripheral buses: General.
C12	PA11	Digital_IO	Signal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: USB_DM. Supported peripheral buses: USB, UART, CAN.
D1	OSC_IN	Digital_IO	Signal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
D2	VSS_5	GND	0V electrical ground return terminal (VSS_5) for internal core logic, I/O drivers, and analog sub-blocks.
D3	VDD_5	Power_In	Primary positive power supply input (VDD_5) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D4	PF2	Digital_IO	Signal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
D5	BOOT0	Digital_IO	Signal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
D6	PB7	Digital_IO	Signal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
D7	PG13	Digital_IO	Signal terminal PG13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG13. Supported peripheral buses: General.
D8	PG10	Digital_IO	Signal terminal PG10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG10. Supported peripheral buses: General.
D9	PD3	Digital_IO	Signal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
D10	PD1	Digital_IO	Signal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
D11	PA10	Digital_IO	Signal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
D12	PA9	Digital_IO	Signal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART.
E1	OSC_OUT	Digital_IO	Signal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
E2	PF3	Digital_IO	Signal terminal PF3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
E3	PF4	Digital_IO	Signal terminal PF4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
E4	PF5	Digital_IO	Signal terminal PF5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
E5	VSS_3	GND	0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
E6	VSS_11	GND	0V electrical ground return terminal (VSS_11) for internal core logic, I/O drivers, and analog sub-blocks.
E7	VSS_10	GND	0V electrical ground return terminal (VSS_10) for internal core logic, I/O drivers, and analog sub-blocks.
E8	PG9	Digital_IO	Signal terminal PG9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG9. Supported peripheral buses: General.
E9	PD2	Digital_IO	Signal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
E10	PD0	Digital_IO	Signal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
E11	PC9	Digital_IO	Signal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E12	PA8	Digital_IO	Signal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
F1	NRST	Digital_IO	Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F2	PF7	Digital_IO	Signal terminal PF7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF7. Supported peripheral buses: ADC.
F3	PF6	Digital_IO	Signal terminal PF6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF6. Supported peripheral buses: ADC.
F4	VDD_4	Power_In	Primary positive power supply input (VDD_4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).

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