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CH351Q (LQFP-64(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH351Q

WCHID: C123779LQFP-64(7x7) · 64 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH351Q (LQFP-64(7x7))1AD222AD213AD204AD195AD186AD177AD168CBE3～CBE09FRAME10TRDY11DEVSEL12INTA13PAR14CBE3～CBE015AD1516AD1417VCC18AD1319AD1220AD1121AD1022AD923AD824CBE3～CBE025AD726AD627AD528AD429AD330AD231AD132AD064AD2363IDSEL62CBE3～CBE061AD2460AD2559AD2658AD2757AD2856AD2955AD3054AD3153VCC52GND51CLK50RST49XI48CTS147DSR146RI145DCD144RXD143RXD042TXD141TXD040CTS039DSR038RI037DCD036RTS135DTR1 TNOW134RTS033DTR0 TNOW0Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.245.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=7.00mm · Pitch e=0.40mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1AD22I/OMultiplexed I/O & Peripheral Pin AD22 (General)
2AD21I/OMultiplexed I/O & Peripheral Pin AD21 (General)
3AD20I/OMultiplexed I/O & Peripheral Pin AD20 (General)
4AD19I/OMultiplexed I/O & Peripheral Pin AD19 (General)
5AD18I/OMultiplexed I/O & Peripheral Pin AD18 (General)
6AD17I/OMultiplexed I/O & Peripheral Pin AD17 (General)
7AD16I/OMultiplexed I/O & Peripheral Pin AD16 (General)
8CBE3～CBE0I/OMultiplexed I/O & Peripheral Pin CBE3～CBE0 (General)
9FRAMEI/OMultiplexed I/O & Peripheral Pin FRAME (General)
10TRDYI/OMultiplexed I/O & Peripheral Pin TRDY (General)
11DEVSELI/OMultiplexed I/O & Peripheral Pin DEVSEL (General)
12INTAI/OMultiplexed I/O & Peripheral Pin INTA (General)
13PARI/OMultiplexed I/O & Peripheral Pin PAR (General)
14CBE3～CBE0I/OMultiplexed I/O & Peripheral Pin CBE3～CBE0 (General)
15AD15I/OMultiplexed I/O & Peripheral Pin AD15 (General)
16AD14I/OMultiplexed I/O & Peripheral Pin AD14 (General)
17VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
18AD13I/OMultiplexed I/O & Peripheral Pin AD13 (General)
19AD12I/OMultiplexed I/O & Peripheral Pin AD12 (General)
20AD11I/OMultiplexed I/O & Peripheral Pin AD11 (General)
21AD10I/OMultiplexed I/O & Peripheral Pin AD10 (General)
22AD9I/OMultiplexed I/O & Peripheral Pin AD9 (General)
23AD8I/OMultiplexed I/O & Peripheral Pin AD8 (General)
24CBE3～CBE0I/OMultiplexed I/O & Peripheral Pin CBE3～CBE0 (General)
25AD7I/OMultiplexed I/O & Peripheral Pin AD7 (General)
26AD6I/OMultiplexed I/O & Peripheral Pin AD6 (General)
27AD5I/OMultiplexed I/O & Peripheral Pin AD5 (General)
28AD4I/OMultiplexed I/O & Peripheral Pin AD4 (General)
29AD3I/OMultiplexed I/O & Peripheral Pin AD3 (General)
30AD2I/OMultiplexed I/O & Peripheral Pin AD2 (General)
31AD1I/OMultiplexed I/O & Peripheral Pin AD1 (General)
32AD0I/OMultiplexed I/O & Peripheral Pin AD0 (General)
33DTR0 TNOW0I/OMultiplexed I/O & Peripheral Pin DTR0 TNOW0 (UART)
34RTS0I/OMultiplexed I/O & Peripheral Pin RTS0 (UART)
35DTR1 TNOW1I/OMultiplexed I/O & Peripheral Pin DTR1 TNOW1 (UART)
36RTS1I/OMultiplexed I/O & Peripheral Pin RTS1 (UART)
37DCD0I/OMultiplexed I/O & Peripheral Pin DCD0 (General)
38RI0I/OMultiplexed I/O & Peripheral Pin RI0 (General)
39DSR0I/OMultiplexed I/O & Peripheral Pin DSR0 (UART)
40CTS0I/OMultiplexed I/O & Peripheral Pin CTS0 (UART)
41TXD0I/OTXD0 (UART)
42TXD1I/OTXD1 (UART)
43RXD0I/ORXD0 (UART)
44RXD1I/ORXD1 (UART)
45DCD1I/OMultiplexed I/O & Peripheral Pin DCD1 (General)
46RI1I/OMultiplexed I/O & Peripheral Pin RI1 (General)
47DSR1I/OMultiplexed I/O & Peripheral Pin DSR1 (UART)
48CTS1I/OMultiplexed I/O & Peripheral Pin CTS1 (UART)
49XII/OXI (RTC/CLK)
50RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
51CLKI/OMultiplexed I/O & Peripheral Pin CLK (General)
52GNDGNDGround Reference Pin (GND)
53VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
54AD31I/OMultiplexed I/O & Peripheral Pin AD31 (General)
55AD30I/OMultiplexed I/O & Peripheral Pin AD30 (General)
56AD29I/OMultiplexed I/O & Peripheral Pin AD29 (General)
57AD28I/OMultiplexed I/O & Peripheral Pin AD28 (General)
58AD27I/OMultiplexed I/O & Peripheral Pin AD27 (General)
59AD26I/OMultiplexed I/O & Peripheral Pin AD26 (General)
60AD25I/OMultiplexed I/O & Peripheral Pin AD25 (General)
61AD24I/OMultiplexed I/O & Peripheral Pin AD24 (General)
62CBE3～CBE0I/OMultiplexed I/O & Peripheral Pin CBE3～CBE0 (General)
63IDSELI/OMultiplexed I/O & Peripheral Pin IDSEL (General)
64AD23I/OMultiplexed I/O & Peripheral Pin AD23 (General)
PIN 1 AD22
I/O
Multiplexed I/O & Peripheral Pin AD22 (General)
Design note: Signal terminal AD22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD22. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH351Q (WCH · LQFP-64(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH351Q (LQFP-64(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH351Q (LQFP-64(7x7)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH351Q (LQFP-64(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH351Q (LQFP-64(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-64(7x7) · 7.00×7.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH351Q (LQFP-64(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH351Q (LQFP-64(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH351
P1 · p01_fig011551×1276px
CH351Q (LQFP-64(7x7)) — 2、特点
2、特点
P2 · p02_fig011052×861px
CH351Q (LQFP-64(7x7)) — 3、封装
3、封装
P2 · p02_fig01P2
CH351Q (LQFP-64(7x7)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P9 · p09_fig012046×1623px
CH351Q (LQFP-64(7x7)) — 这是基于CH351 芯片的PCI 双通道串口的电路。U3 和U4 是RS232 电平转换芯片75232，P3 和P4 是10 脚双排针或者DB9 插针。晶体X1 用于时钟振荡电路。电容C0 和C11～C13 用于电源退耦，C11～ C13 是容量为0.1uF 的独石或者高频瓷片电容，分别就近并联在CH351 的电源引脚或者75232 芯片的 电源引脚上。
这是基于CH351 芯片的PCI 双通道串口的电路。U3 和U4 是RS232 电平转换芯片75232，P3 和P4 是10 脚双排针或者DB9 插针。晶体X1 用于时钟振荡电路。电容C0 和C11～C13 用于电源退耦，C11～ C13 是容量为0.1uF 的独石或者高频瓷片电容，分别就近并联在CH351 的电源引脚或者75232 芯片的 电源引脚上。
P9 · p09_fig01P9
CH351Q (LQFP-64(7x7)) — Datasheet Page 9 (p09_fig01)
Datasheet Page 9 (p09_fig01)

Technical Specifications & Part Details (CH351Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH351Q (LQFP-64(7x7)) is a 64-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1184MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64(7x7))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-64(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.40mm
Pad Size (W × L)Level B
0.24 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-64(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH351Q (LQFP-64(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH351Q (LQFP-64(7x7))?

Manufactured by WCH, the CH351Q is housed in a LQFP-64(7x7) package with 64 pins and a 0.40 mm lead pitch. Key pins include: 1 (AD22: Multiplexed I/O & Peripheral Pin AD22 (General)), 2 (AD21: Multiplexed I/O & Peripheral Pin AD21 (General)), 3 (AD20: Multiplexed I/O & Peripheral Pin AD20 (General)), 4 (AD19: Multiplexed I/O & Peripheral Pin AD19 (General)), 5 (AD18: Multiplexed I/O & Peripheral Pin AD18 (General)), 6 (AD17: Multiplexed I/O & Peripheral Pin AD17 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH351Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH351Q (LQFP-64(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.40 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH351Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH351Q (WCH, LQFP-64(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & CH351 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1AD22Digital_IOSignal terminal AD22 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD22. Supported peripheral buses: General.
2AD21Digital_IOSignal terminal AD21 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD21. Supported peripheral buses: General.
3AD20Digital_IOSignal terminal AD20 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD20. Supported peripheral buses: General.
4AD19Digital_IOSignal terminal AD19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD19. Supported peripheral buses: General.
5AD18Digital_IOSignal terminal AD18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD18. Supported peripheral buses: General.
6AD17Digital_IOSignal terminal AD17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD17. Supported peripheral buses: General.
7AD16Digital_IOSignal terminal AD16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD16. Supported peripheral buses: General.
8CBE3～CBE0Digital_IOSignal terminal CBE3～CBE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CBE3～CBE0. Supported peripheral buses: General.
9FRAMEDigital_IOSignal terminal FRAME (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FRAME. Supported peripheral buses: General.
10TRDYDigital_IOSignal terminal TRDY (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TRDY. Supported peripheral buses: General.
11DEVSELDigital_IOSignal terminal DEVSEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DEVSEL. Supported peripheral buses: General.
12INTADigital_IOSignal terminal INTA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INTA. Supported peripheral buses: General.
13PARDigital_IOSignal terminal PAR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PAR. Supported peripheral buses: General.
14CBE3～CBE0Digital_IOSignal terminal CBE3～CBE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CBE3～CBE0. Supported peripheral buses: General.
15AD15Digital_IOSignal terminal AD15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD15. Supported peripheral buses: General.
16AD14Digital_IOSignal terminal AD14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD14. Supported peripheral buses: General.
17VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
18AD13Digital_IOSignal terminal AD13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD13. Supported peripheral buses: General.
19AD12Digital_IOSignal terminal AD12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD12. Supported peripheral buses: General.
20AD11Digital_IOSignal terminal AD11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD11. Supported peripheral buses: General.
21AD10Digital_IOSignal terminal AD10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD10. Supported peripheral buses: General.
22AD9Digital_IOSignal terminal AD9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD9. Supported peripheral buses: General.
23AD8Digital_IOSignal terminal AD8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD8. Supported peripheral buses: General.
24CBE3～CBE0Digital_IOSignal terminal CBE3～CBE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CBE3～CBE0. Supported peripheral buses: General.
25AD7Digital_IOSignal terminal AD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD7. Supported peripheral buses: General.
26AD6Digital_IOSignal terminal AD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD6. Supported peripheral buses: General.
27AD5Digital_IOSignal terminal AD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD5. Supported peripheral buses: General.
28AD4Digital_IOSignal terminal AD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD4. Supported peripheral buses: General.
29AD3Digital_IOSignal terminal AD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD3. Supported peripheral buses: General.
30AD2Digital_IOSignal terminal AD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD2. Supported peripheral buses: General.
31AD1Digital_IOSignal terminal AD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD1. Supported peripheral buses: General.
32AD0Digital_IOSignal terminal AD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD0. Supported peripheral buses: General.
33DTR0 TNOW0Digital_IOSignal terminal DTR0 TNOW0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR0 TNOW0. Supported peripheral buses: UART.
34RTS0Digital_IOSignal terminal RTS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS0. Supported peripheral buses: UART.
35DTR1 TNOW1Digital_IOSignal terminal DTR1 TNOW1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR1 TNOW1. Supported peripheral buses: UART.
36RTS1Digital_IOSignal terminal RTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS1. Supported peripheral buses: UART.
37DCD0Digital_IOSignal terminal DCD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD0. Supported peripheral buses: General.
38RI0Digital_IOSignal terminal RI0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI0. Supported peripheral buses: General.
39DSR0Digital_IOSignal terminal DSR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR0. Supported peripheral buses: UART.
40CTS0Digital_IOSignal terminal CTS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0. Supported peripheral buses: UART.
41TXD0Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
42TXD1Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
43RXD0Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
44RXD1Digital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
45DCD1Digital_IOSignal terminal DCD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD1. Supported peripheral buses: General.
46RI1Digital_IOSignal terminal RI1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI1. Supported peripheral buses: General.
47DSR1Digital_IOSignal terminal DSR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR1. Supported peripheral buses: UART.
48CTS1Digital_IOSignal terminal CTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1. Supported peripheral buses: UART.
49XIDigital_IO12 MHz crystal oscillator input (XI); requires a 22pF load capacitor to GND (internally clocked on CH340C).
50RSTDigital_IOSignal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
51CLKDigital_IOSignal terminal CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLK. Supported peripheral buses: General.
52GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
53VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
54AD31Digital_IOSignal terminal AD31 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD31. Supported peripheral buses: General.
55AD30Digital_IOSignal terminal AD30 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD30. Supported peripheral buses: General.
56AD29Digital_IOSignal terminal AD29 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD29. Supported peripheral buses: General.
57AD28Digital_IOSignal terminal AD28 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD28. Supported peripheral buses: General.
58AD27Digital_IOSignal terminal AD27 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD27. Supported peripheral buses: General.
59AD26Digital_IOSignal terminal AD26 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD26. Supported peripheral buses: General.
60AD25Digital_IOSignal terminal AD25 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD25. Supported peripheral buses: General.
61AD24Digital_IOSignal terminal AD24 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD24. Supported peripheral buses: General.
62CBE3～CBE0Digital_IOSignal terminal CBE3～CBE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CBE3～CBE0. Supported peripheral buses: General.
63IDSELDigital_IOSignal terminal IDSEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IDSEL. Supported peripheral buses: General.
64AD23Digital_IOSignal terminal AD23 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD23. Supported peripheral buses: General.
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