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STM32H7A3VIT6Q (LQFP-100(14x14)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32H7A3VIT6Q

STLQFP-100(14x14) · 100 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32H7A3VIT6Q (LQFP-100(14x14))1PE22PE43PE54VDD5VBAT6PC137PC14-OSC32_O8PC15-OSC32_O9VSSMPS10VLXSMPS11VDDSMPS12VFBSMPS13PH0-OSC_IN14PH1-OSC_OUT15NRST16PC017PC118PC2_C19PC3_C20VDD21VSS22VSSA23VREF+24VDDA25PA026PA127PA228PA329VSS30VDD31PA432PA533PA634PA735PC436PC537PB038PB139PB240PE741PE842PB1043PB1144VCAP45VSS46VDDLDO47VDD48PB1249PB1350PB14100VDD99VDDLDO98VSS97PE096PB995PB894BOOT093PB792PB691PB590PB489PB388VDD87PD586PD485PD384PD283PD182PD081PC1280PC1179PC1078PA1577PA1476VDD33USB75VDD74VDDLDO73VSS72VCAP71PA1370PA1269PA1168PA1067PA966PA865PC964PC863PC762PC661PD1560PD1459VDD58VSS57PD1356PD1255PD1154PD1053PD952PD851PB15Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100E=14.00mm · Pitch e=0.50mmD=14.00mm-13-11-9-7-5-3-1135791113131197531-1-3-5-7-9-11-13mm
3. 3D CAD MODEL
Package Body: 14.00mm × 14.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
2PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
3PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
5VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
6PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
7PC14-OSC32_ONI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_ON (RTC/CLK)
8PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
9VSSMPSGNDGround Reference Pin (VSSMPS)
10VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
11VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
12VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
13PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
14PH1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)
15NRSTISystem Enable & Hardware Reset (NRST)
16PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
17PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
18PC2_CI/OMultiplexed I/O & Peripheral Pin PC2_C (General)
19PC3_CI/OMultiplexed I/O & Peripheral Pin PC3_C (General)
20VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
21VSSGNDGround Reference Pin (VSS)
22VSSAGNDGround Reference Pin (VSSA)
23VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
24VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
25PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
26PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
27PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
28PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
29VSSGNDGround Reference Pin (VSS)
30VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
31PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
32PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
33PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
34PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
35PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
36PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
37PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
38PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
39PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
40PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
41PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
42PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
43PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
44VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
45VSSGNDGround Reference Pin (VSS)
46VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
47VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
48PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
49PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
50PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
51PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
52PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
53PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
54PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
55PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
56PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
57PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
58VSSGNDGround Reference Pin (VSS)
59VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
60PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
61PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
62PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
63PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
64PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
65PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
66PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
67PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
68PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
69PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
70PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
71PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
72VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
73VSSGNDGround Reference Pin (VSS)
74VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
75VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
76VDD33USBPowerPower Supply Input (VDD33USB — 3.3V VDD (Max 4.0V))
77PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
78PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
79PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
80PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
81PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
82PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
83PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
84PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
85PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
86PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
87PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
88VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
89PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
90PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
91PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
92PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
93PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
94BOOT0IInput-Only Pin BOOT0 (General)
95PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
96PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
97PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
98VSSGNDGround Reference Pin (VSS)
99VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
100VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
PIN 1 PE2
I/O
Multiplexed I/O & Peripheral Pin PE2 (General)
Design note: Signal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 36 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32H7A3VIT6Q (ST · LQFP-100(14x14))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32H7A3VIT6Q (LQFP-100(14x14)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32H7A3VIT6Q (LQFP-100(14x14)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32H7A3VIT6Q (LQFP-100(14x14)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32H7A3VIT6Q (LQFP-100(14x14)) - 4. Package Dimensions (D×E×A)
LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32H7A3VIT6Q (LQFP-100(14x14)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32H7A3VIT6Q (LQFP-100(14x14)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (36 figures · Page 1/3)
Showing 1–12 of 36 uncropped original figures for STM32H7A3VIT / STM32H7A3IGT / STM32H7A3NIH
P1 · p01_fig01EXACT PACKAGE
STM32H7A3VIT6Q (LQFP-100(14x14)) — WLCSP132 (4.57 X 4.37 mm) | LQFP64 (10 x 10 mm) | LQFP100 (14 x 14 mm) | LQFP144 (20x20 mm) | LQFP176 (24 x 24 mm) | TFBGA100 | (8 x 8 mm) TFBGA216 (13x13 mm) | TFBGA225 (13x13 mm) | FBGA | UFBGA169 | (7 x 7 mm) UFBGA176+25 | (10x10 mm) | F
WLCSP132 (4.57 X 4.37 mm) | LQFP64 (10 x 10 mm) | LQFP100 (14 x 14 mm) | LQFP144 (20x20 mm) | LQFP176 (24 x 24 mm) | TFBGA100 | (8 x 8 mm) TFBGA216 (13x13 mm) | TFBGA225 (13x13 mm) | FBGA | UFBGA169 | (7 x 7 mm) UFBGA176+25 | (10x10 mm) | F
P36 · p36_fig01EXACT PACKAGE
STM32H7A3VIT6Q (LQFP-100(14x14)) — Figure 5. LQFP100 (STM32H7A3xI/G with SMPS) pinout
Figure 5. LQFP100 (STM32H7A3xI/G with SMPS) pinout
P37 · p37_fig01EXACT PACKAGE
STM32H7A3VIT6Q (LQFP-100(14x14)) — Figure 6. LQFP100 (STM32H7A3xI/G without SMPS) pinout
Figure 6. LQFP100 (STM32H7A3xI/G without SMPS) pinout
P186 · p186_fig01EXACT PACKAGE
STM32H7A3VIT6Q (LQFP-100(14x14)) — Figure 85. LQFP100 - Outline
Figure 85. LQFP100 - Outline
P187 · p187_fig01EXACT PACKAGE
STM32H7A3VIT6Q (LQFP-100(14x14)) — Figure 86. LQFP100 - Recommended footprint
Figure 86. LQFP100 - Recommended footprint
P36 · p36_fig01P36
STM32H7A3VIT6Q (LQFP-100(14x14)) — Datasheet Page 36 (p36_fig01)
Datasheet Page 36 (p36_fig01)
P48 · p48_fig011957×901px
STM32H7A3VIT6Q (LQFP-100(14x14)) — DFSDM1_DATIN3,
DFSDM1_DATIN3,
P79 · p79_fig011500×2357px
STM32H7A3VIT6Q (LQFP-100(14x14)) — Figure 21. Power supply scheme
Figure 21. Power supply scheme
P79 · p79_fig01P79
STM32H7A3VIT6Q (LQFP-100(14x14)) — Datasheet Page 79 (p79_fig01)
Datasheet Page 79 (p79_fig01)
P108 · p108_fig011371×460px
STM32H7A3VIT6Q (LQFP-100(14x14)) — Figure 32. Typical application with an 8 MHz crystal
Figure 32. Typical application with an 8 MHz crystal
P149 · p149_fig011465×573px
STM32H7A3VIT6Q (LQFP-100(14x14)) — Figure 56. Typical connection diagram using the ADC
Figure 56. Typical connection diagram using the ADC
P149 · p149_fig021133×781px
STM32H7A3VIT6Q (LQFP-100(14x14)) — Figure 57. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 57. Power supply and reference decoupling (VREF+ not connected to VDDA)
Page 1 / 3 (36 extracted figures)

Technical Specifications & Part Details (STM32H7A3VIT6Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32H7A3VIT6Q (LQFP-100(14x14)) is a 100-pin embedded microcontroller unit (mcu) featuring a 14.00 × 14.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
280 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-100(14x14))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32H7A3VIT / STM32H7A3IGT / STM32H7A3NIH (10)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (LQFP-100(14x14))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.20 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-100(14x14)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32H7A3VIT6Q (LQFP-100(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32H7A3VIT6Q (LQFP-100(14x14))?

Manufactured by ST, the STM32H7A3VIT6Q is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PE4: Multiplexed I/O & Peripheral Pin PE4 (General)), 3 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), 4 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), 5 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 6 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32H7A3VIT6Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H7A3VIT6Q (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H7A3VIT6Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H7A3VIT6Q (ST, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32H7A3VIT / STM32H7A3IGT / STM32H7A3NIH Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
2PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
3PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
5VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
6PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
7PC14-OSC32_ONDigital_IOSignal terminal PC14-OSC32_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_ON. Supported peripheral buses: RTC/CLK.
8PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
9VSSMPSGND0V electrical ground return terminal (VSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
10VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
11VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
12VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
13PH0-OSC_INDigital_IOSignal terminal PH0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK.
14PH1-OSC_OUTDigital_IOSignal terminal PH1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1-OSC_OUT. Supported peripheral buses: RTC/CLK.
15NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
16PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
17PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
18PC2_CDigital_IOSignal terminal PC2_C (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2_C. Supported peripheral buses: General.
19PC3_CDigital_IOSignal terminal PC3_C (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3_C. Supported peripheral buses: General.
20VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
21VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
22VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
23VREF+AnalogSignal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General.
24VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
25PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
26PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
27PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
28PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
29VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
30VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
31PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
32PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
33PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
34PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
35PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
36PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
37PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
38PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
39PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
40PE7Digital_IOSignal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
41PE8Digital_IOSignal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: General.
42PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
43PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
44VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
45VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
46VDDLDOPower_InPrimary positive power supply input (VDDLDO) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
47VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
48PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
49PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
50PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
51PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
52PD8Digital_IOSignal terminal PD8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD8. Supported peripheral buses: General.
53PD9Digital_IOSignal terminal PD9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD9. Supported peripheral buses: General.
54PD10Digital_IOSignal terminal PD10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: General.
55PD11Digital_IOSignal terminal PD11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: General.
56PD12Digital_IOSignal terminal PD12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: General.
57PD13Digital_IOSignal terminal PD13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: General.
58VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
59VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
60PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
61PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
62PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
63PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
64PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
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